JPS54109733A - Synchronous control system for interface device - Google Patents

Synchronous control system for interface device

Info

Publication number
JPS54109733A
JPS54109733A JP1722478A JP1722478A JPS54109733A JP S54109733 A JPS54109733 A JP S54109733A JP 1722478 A JP1722478 A JP 1722478A JP 1722478 A JP1722478 A JP 1722478A JP S54109733 A JPS54109733 A JP S54109733A
Authority
JP
Japan
Prior art keywords
cpu1
port
signal
cpu
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1722478A
Other languages
Japanese (ja)
Inventor
Yutaka Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP1722478A priority Critical patent/JPS54109733A/en
Publication of JPS54109733A publication Critical patent/JPS54109733A/en
Pending legal-status Critical Current

Links

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  • Information Transfer Systems (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To decrease the number of the line for the timing signal and thus to facilitate the circuit design by synchronizing the interface device with CPU only when the information is transferred between CPU and the peripheral units with the nonsynchronous transfer given usually with CPU.
CONSTITUTION: I/O port 2 is provided between CPU1 and the peripheral unit such as key input part 3 or the like to interface the order indicating the transfer of the information given from CPU1 and part 3. In such port 2, CPU1 and port 2 are connected via data bus 4 and address bus 5, and port 2 and part 3 are connected via data bus 6 and 7. Furthermore, control signal J is transmitted to port 2 from CPU1 via signal line 8, and the order code of signal J is decoded at port 2. And the synchronous pulse is generated based on signal J in case the information transmission order is given from CPU1. With this synchronous pulse, the synchronization is secured with CPU1 but not secured usually.
COPYRIGHT: (C)1979,JPO&Japio
JP1722478A 1978-02-16 1978-02-16 Synchronous control system for interface device Pending JPS54109733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1722478A JPS54109733A (en) 1978-02-16 1978-02-16 Synchronous control system for interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1722478A JPS54109733A (en) 1978-02-16 1978-02-16 Synchronous control system for interface device

Publications (1)

Publication Number Publication Date
JPS54109733A true JPS54109733A (en) 1979-08-28

Family

ID=11937971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1722478A Pending JPS54109733A (en) 1978-02-16 1978-02-16 Synchronous control system for interface device

Country Status (1)

Country Link
JP (1) JPS54109733A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285360A (en) * 1985-10-09 1987-04-18 Mitsubishi Electric Corp Serial data input/output circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285360A (en) * 1985-10-09 1987-04-18 Mitsubishi Electric Corp Serial data input/output circuit

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