JPS5644925A - Control system of data processing system - Google Patents

Control system of data processing system

Info

Publication number
JPS5644925A
JPS5644925A JP11942179A JP11942179A JPS5644925A JP S5644925 A JPS5644925 A JP S5644925A JP 11942179 A JP11942179 A JP 11942179A JP 11942179 A JP11942179 A JP 11942179A JP S5644925 A JPS5644925 A JP S5644925A
Authority
JP
Japan
Prior art keywords
dma
signal
generated
dma request
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11942179A
Other languages
Japanese (ja)
Inventor
Yoshiaki Kitatsume
Hiromichi Fujisawa
Eiji Ohira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11942179A priority Critical patent/JPS5644925A/en
Publication of JPS5644925A publication Critical patent/JPS5644925A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To suppress the synchronizing signal transmitted from the central processing unit to suppress the DMA request of other devices when one device performs DMA, in direct high-speed transfer (DMA) between the cetral processing unit having a main memory and plural devices.
CONSTITUTION: If a certain device issues DMA request S3 when DMA permission signal S1 is "1", DMA request signal S4 is generated synchronously with DMA request synchronizing signal S2 and is transmitted to the central processing unit. Service signal generating circuit 80 generates DMA service signal S7 for DMA. Now, even if another device issues DMA request (f) when DMA service signal S7 is generated to a certain device, DMA request signal (g) is not generated because the DMA request synchronizing signal is not generated from AND circuit 83. Therefore, transfer data from the I/O device performing DMA is not lost.
COPYRIGHT: (C)1981,JPO&Japio
JP11942179A 1979-09-19 1979-09-19 Control system of data processing system Pending JPS5644925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11942179A JPS5644925A (en) 1979-09-19 1979-09-19 Control system of data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11942179A JPS5644925A (en) 1979-09-19 1979-09-19 Control system of data processing system

Publications (1)

Publication Number Publication Date
JPS5644925A true JPS5644925A (en) 1981-04-24

Family

ID=14761035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11942179A Pending JPS5644925A (en) 1979-09-19 1979-09-19 Control system of data processing system

Country Status (1)

Country Link
JP (1) JPS5644925A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6220807A (en) * 1985-07-18 1987-01-29 Kobe Steel Ltd Iron making method by melt reduction of iron ore
JPS63225847A (en) * 1987-03-13 1988-09-20 Fujitsu Ltd Input/output adapter
JPS63231664A (en) * 1987-03-20 1988-09-27 Fujitsu Ltd Input/output control adapter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6220807A (en) * 1985-07-18 1987-01-29 Kobe Steel Ltd Iron making method by melt reduction of iron ore
JPH0581641B2 (en) * 1985-07-18 1993-11-15 Kobe Steel Ltd
JPS63225847A (en) * 1987-03-13 1988-09-20 Fujitsu Ltd Input/output adapter
JPS63231664A (en) * 1987-03-20 1988-09-27 Fujitsu Ltd Input/output control adapter

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