JPS5611546A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS5611546A
JPS5611546A JP8771979A JP8771979A JPS5611546A JP S5611546 A JPS5611546 A JP S5611546A JP 8771979 A JP8771979 A JP 8771979A JP 8771979 A JP8771979 A JP 8771979A JP S5611546 A JPS5611546 A JP S5611546A
Authority
JP
Japan
Prior art keywords
information
transfer
controller
unit
reliability
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8771979A
Other languages
Japanese (ja)
Inventor
Kunio Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8771979A priority Critical patent/JPS5611546A/en
Publication of JPS5611546A publication Critical patent/JPS5611546A/en
Pending legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To increase the reliability, by decreasing the length and number of signal lines, through the transfer of the information to the information processor not via the software, by using the direct access unit from the cyclic digital information transmission unit.
CONSTITUTION: The word serial bit parallel information signal is fed to the input controller 71 of the direct memory access unit DMA7 from the cyclic digital information transmission unit CDC6. Further, when the controller 73 detects it via the gate circuit 72, the controller 73 performs transfer of information to the information processor 8 and when it is finished, the transfer of information to the information processor 9 is made. Thus, the information from the unit CDT6 is transferred to the units 8, 9 not via the software, allowing to decrease the length and number of the signal lines and to increase the reliability.
COPYRIGHT: (C)1981,JPO&Japio
JP8771979A 1979-07-11 1979-07-11 Information processing system Pending JPS5611546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8771979A JPS5611546A (en) 1979-07-11 1979-07-11 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8771979A JPS5611546A (en) 1979-07-11 1979-07-11 Information processing system

Publications (1)

Publication Number Publication Date
JPS5611546A true JPS5611546A (en) 1981-02-04

Family

ID=13922706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8771979A Pending JPS5611546A (en) 1979-07-11 1979-07-11 Information processing system

Country Status (1)

Country Link
JP (1) JPS5611546A (en)

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