JPS5536830A - Multiprocessor control system of copier - Google Patents

Multiprocessor control system of copier

Info

Publication number
JPS5536830A
JPS5536830A JP10966178A JP10966178A JPS5536830A JP S5536830 A JPS5536830 A JP S5536830A JP 10966178 A JP10966178 A JP 10966178A JP 10966178 A JP10966178 A JP 10966178A JP S5536830 A JPS5536830 A JP S5536830A
Authority
JP
Japan
Prior art keywords
cpu
bus line
changeover
circuit
copier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10966178A
Other languages
Japanese (ja)
Inventor
Masao Hosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP10966178A priority Critical patent/JPS5536830A/en
Publication of JPS5536830A publication Critical patent/JPS5536830A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Or Security For Electrophotography (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To enable data exchange between one CPU and another without restricting action of each CPU more than necessity, by connecting a plurality of CPU's through a bus line changeover device, and delivering stroboscopic signals for these changeover from each CPU input and output port.
CONSTITUTION: An embodiment example having 3 CPU's is shown in the drawing. Bus line 4 is connected to bus line 4a... and disconnected from this through bus line changeover devices 5 and 6 when necessary. Since bus line 4a... is usually disconnected, each CPU1... can be run freely without any restriction from others. For example, when data are transferred from CPU1 to CPU2, a stroboscopic signal produced from the I/0 port of CPU1 is transmitted via an OR circuit to bus line changeover device 5 to connect bus lines 4a and 4b, while CPU2 is held through OR circuit 10 and the line of CPU2 is stopped till data transfer is finished.
COPYRIGHT: (C)1980,JPO&Japio
JP10966178A 1978-09-08 1978-09-08 Multiprocessor control system of copier Pending JPS5536830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10966178A JPS5536830A (en) 1978-09-08 1978-09-08 Multiprocessor control system of copier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10966178A JPS5536830A (en) 1978-09-08 1978-09-08 Multiprocessor control system of copier

Publications (1)

Publication Number Publication Date
JPS5536830A true JPS5536830A (en) 1980-03-14

Family

ID=14515944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10966178A Pending JPS5536830A (en) 1978-09-08 1978-09-08 Multiprocessor control system of copier

Country Status (1)

Country Link
JP (1) JPS5536830A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132873U (en) * 1989-04-10 1990-11-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02132873U (en) * 1989-04-10 1990-11-05

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