JPS55910A - Multiple computer system - Google Patents

Multiple computer system

Info

Publication number
JPS55910A
JPS55910A JP7213978A JP7213978A JPS55910A JP S55910 A JPS55910 A JP S55910A JP 7213978 A JP7213978 A JP 7213978A JP 7213978 A JP7213978 A JP 7213978A JP S55910 A JPS55910 A JP S55910A
Authority
JP
Japan
Prior art keywords
line
lbc
communication
transmitted
lbcs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7213978A
Other languages
Japanese (ja)
Inventor
Toshiyuki Ide
Shigeo Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7213978A priority Critical patent/JPS55910A/en
Publication of JPS55910A publication Critical patent/JPS55910A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To enable the system to carry on its operation on the whole even if a random LBC gets out of order, by decentralizing communication bus controllers LBC to each central processor CPU and the system operation board.
CONSTITUTION: The multiple computer system is provided with several communication buses 1; signals are transmitted through the 1st and 2nd lines 11 and 12, and data are through the 3rd line 13. Between communication buses 1, and CPUs 31 to 33 and system operation board 4, LBCs 21 to 24 are provided for the processing of mutual communication functions through respective LBCs 21 to 24. When no signals are transmitted via the lst line 11 and 2nd lines 12 of the communication buses, a siganl is forcibly transmitted via the 2nd line and after stand-by time equivalent to the priority of LBC at that time elapses, a check on the lst line 11 is made, so that when no signal is transmitted, processing will be performed by exclusively using communication bus I.
COPYRIGHT: (C)1980,JPO&Japio
JP7213978A 1978-06-16 1978-06-16 Multiple computer system Pending JPS55910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7213978A JPS55910A (en) 1978-06-16 1978-06-16 Multiple computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7213978A JPS55910A (en) 1978-06-16 1978-06-16 Multiple computer system

Publications (1)

Publication Number Publication Date
JPS55910A true JPS55910A (en) 1980-01-07

Family

ID=13480648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7213978A Pending JPS55910A (en) 1978-06-16 1978-06-16 Multiple computer system

Country Status (1)

Country Link
JP (1) JPS55910A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729130A (en) * 1980-07-29 1982-02-17 Fujitsu Ltd Common-bus interface protecting system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4973043A (en) * 1972-11-14 1974-07-15
JPS5081646A (en) * 1973-11-21 1975-07-02

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4973043A (en) * 1972-11-14 1974-07-15
JPS5081646A (en) * 1973-11-21 1975-07-02

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729130A (en) * 1980-07-29 1982-02-17 Fujitsu Ltd Common-bus interface protecting system
JPH0157376B2 (en) * 1980-07-29 1989-12-05 Fujitsu Ltd

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