JPS55153024A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS55153024A
JPS55153024A JP5929279A JP5929279A JPS55153024A JP S55153024 A JPS55153024 A JP S55153024A JP 5929279 A JP5929279 A JP 5929279A JP 5929279 A JP5929279 A JP 5929279A JP S55153024 A JPS55153024 A JP S55153024A
Authority
JP
Japan
Prior art keywords
bus
input
buffer memory
dma
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5929279A
Other languages
Japanese (ja)
Inventor
Shoji Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5929279A priority Critical patent/JPS55153024A/en
Publication of JPS55153024A publication Critical patent/JPS55153024A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To improve the processing performance of the entire system by processing input-output data between one buffer memory and CPU while DMA (Direct Memory Access) transfer of input-output data is in process between the other buffer memory and an input-output equipment.
CONSTITUTION: To the primary bus 51, central processor 1, main memory 2 and low-speed input-output equipment 3 requesting program transfer are connected. To the secondary bus 52, on the other hand, DMA controller 6, buffer memory 7 and high-speed input-output equipment 4 requesting DMA transfer are connected. Further, the primary bus 51 and the secondary bus 52 are coupled with each other via bus switch 8. Then, bus switch 8 functions to disconnect the secondary bus 52 from the primary bus 51 in response to the secondary-bus occupation request signal sent out from DMA controller 6.
COPYRIGHT: (C)1980,JPO&Japio
JP5929279A 1979-05-15 1979-05-15 Bus control system Pending JPS55153024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5929279A JPS55153024A (en) 1979-05-15 1979-05-15 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5929279A JPS55153024A (en) 1979-05-15 1979-05-15 Bus control system

Publications (1)

Publication Number Publication Date
JPS55153024A true JPS55153024A (en) 1980-11-28

Family

ID=13109153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5929279A Pending JPS55153024A (en) 1979-05-15 1979-05-15 Bus control system

Country Status (1)

Country Link
JP (1) JPS55153024A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581256A (en) * 1981-06-26 1983-01-06 Fujitsu Ltd Memroy access control system
JPS5819969A (en) * 1981-07-30 1983-02-05 Fujitsu Ltd Memory access controlling system
JPS59123030A (en) * 1982-12-29 1984-07-16 Fujitsu Ltd Data processor
JPS60200356A (en) * 1984-03-23 1985-10-09 Nec Corp Dma transfer control system
JPS616754A (en) * 1984-06-20 1986-01-13 Sanyo Electric Co Ltd Direct memory access transfer system
JPS61262870A (en) * 1985-05-16 1986-11-20 Mitsubishi Electric Corp Bus controlling system
JPS6337453A (en) * 1986-08-01 1988-02-18 Matsushita Electric Ind Co Ltd Bus switch device
JPH01100653A (en) * 1987-10-14 1989-04-18 Fuji Facom Corp System for transferring data of i/o processor
JPH01194050A (en) * 1988-01-29 1989-08-04 Meidensha Corp Circuit constitution for dma device
JPH01276262A (en) * 1988-04-28 1989-11-06 Yamatake Honeywell Co Ltd Dma device
US4991217A (en) * 1984-11-30 1991-02-05 Ibm Corporation Dual processor speech recognition system with dedicated data acquisition bus
JPH03240854A (en) * 1990-11-21 1991-10-28 Hitachi Ltd Microcomputer
JPH0683752A (en) * 1992-06-19 1994-03-25 Teac Corp Composite storage device connected to host device
JP2007508601A (en) * 2003-07-22 2007-04-05 マイクロン・テクノロジー・インコーポレーテッド Apparatus and method for direct memory access in a hub-based storage system

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS581256A (en) * 1981-06-26 1983-01-06 Fujitsu Ltd Memroy access control system
JPH035619B2 (en) * 1981-06-26 1991-01-28 Fujitsu Ltd
JPH0256692B2 (en) * 1981-07-30 1990-11-30 Fujitsu Ltd
JPS5819969A (en) * 1981-07-30 1983-02-05 Fujitsu Ltd Memory access controlling system
JPS59123030A (en) * 1982-12-29 1984-07-16 Fujitsu Ltd Data processor
JPS60200356A (en) * 1984-03-23 1985-10-09 Nec Corp Dma transfer control system
JPS616754A (en) * 1984-06-20 1986-01-13 Sanyo Electric Co Ltd Direct memory access transfer system
US4991217A (en) * 1984-11-30 1991-02-05 Ibm Corporation Dual processor speech recognition system with dedicated data acquisition bus
JPS61262870A (en) * 1985-05-16 1986-11-20 Mitsubishi Electric Corp Bus controlling system
JPS6337453A (en) * 1986-08-01 1988-02-18 Matsushita Electric Ind Co Ltd Bus switch device
JPH01100653A (en) * 1987-10-14 1989-04-18 Fuji Facom Corp System for transferring data of i/o processor
JPH01194050A (en) * 1988-01-29 1989-08-04 Meidensha Corp Circuit constitution for dma device
JPH01276262A (en) * 1988-04-28 1989-11-06 Yamatake Honeywell Co Ltd Dma device
JPH03240854A (en) * 1990-11-21 1991-10-28 Hitachi Ltd Microcomputer
JPH0638249B2 (en) * 1990-11-21 1994-05-18 株式会社日立製作所 Microcomputer
JPH0683752A (en) * 1992-06-19 1994-03-25 Teac Corp Composite storage device connected to host device
JP2007508601A (en) * 2003-07-22 2007-04-05 マイクロン・テクノロジー・インコーポレーテッド Apparatus and method for direct memory access in a hub-based storage system

Similar Documents

Publication Publication Date Title
JPS55153024A (en) Bus control system
JPS57105879A (en) Control system for storage device
JPS5717014A (en) Numerical controller
JPS5672752A (en) Controller for occupation of common bus line
JPS54127239A (en) Input-output control system
JPS57141768A (en) High speed transferring device for video information
JPS57176465A (en) Main storage control system
JPS5621222A (en) Memory extension system
JPS54156433A (en) Buffer memory control system
JPS54161854A (en) Input/output control system for information processor
JPS54129937A (en) Bus control system
JPS5525110A (en) Data processing system
JPS5563423A (en) Data transfer system
JPS5674738A (en) Transfer system of display data
JPS5338236A (en) Multi-computer system
JPS54101235A (en) Operational processor
JPS55157027A (en) Input and output transfer control unit
JPS5783864A (en) Multiprocessor system
JPS5759222A (en) Dma data transfer system
JPS5489456A (en) Buffer open control processing method
JPS5685176A (en) Picture data compressing device
JPS5644925A (en) Control system of data processing system
JPS5542341A (en) Data transfer system
JPS5667430A (en) Dma control device
EP0278263A3 (en) Multiple bus dma controller