JPS5621222A - Memory extension system - Google Patents

Memory extension system

Info

Publication number
JPS5621222A
JPS5621222A JP9671579A JP9671579A JPS5621222A JP S5621222 A JPS5621222 A JP S5621222A JP 9671579 A JP9671579 A JP 9671579A JP 9671579 A JP9671579 A JP 9671579A JP S5621222 A JPS5621222 A JP S5621222A
Authority
JP
Japan
Prior art keywords
memory
ram5
dma transfer
dma
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9671579A
Other languages
Japanese (ja)
Inventor
Junichi Komuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP9671579A priority Critical patent/JPS5621222A/en
Publication of JPS5621222A publication Critical patent/JPS5621222A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable high speed processing, by executing the data transfer by DMA transfer system, between RAMs for main memory and auxiliary use.
CONSTITUTION: The CPU1 is connected to the main memory 2 and DMA controller 3 via the data bus DB and the address bus AB. The memory 2 performs data transfer of DMA transfer system with RAM5 being the auxiliary memory under the control of the controller 3. The head address and number of transferred words performing DMA transfer of RAM5 is preset at DMA transfer by CPU1. The data transfer between the memory 1 and RAM5 is possible for the execution, by changing the program input by CPU, between an arbitrary area of RAM and the memory, then high speed processing is enabled and the extension of memory capacity can simply be made.
COPYRIGHT: (C)1981,JPO&Japio
JP9671579A 1979-07-31 1979-07-31 Memory extension system Pending JPS5621222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9671579A JPS5621222A (en) 1979-07-31 1979-07-31 Memory extension system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9671579A JPS5621222A (en) 1979-07-31 1979-07-31 Memory extension system

Publications (1)

Publication Number Publication Date
JPS5621222A true JPS5621222A (en) 1981-02-27

Family

ID=14172434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9671579A Pending JPS5621222A (en) 1979-07-31 1979-07-31 Memory extension system

Country Status (1)

Country Link
JP (1) JPS5621222A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116830A (en) * 1982-12-24 1984-07-05 Hitachi Micro Comput Eng Ltd Microcomputer system
JPS59139428A (en) * 1982-12-28 1984-08-10 Fujitsu Ltd Direct memory access system
JPS59167761A (en) * 1983-03-14 1984-09-21 Hitachi Ltd Computer system
JPS63113653A (en) * 1986-10-30 1988-05-18 Hitachi Ltd Semiconductor memory controller

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59116830A (en) * 1982-12-24 1984-07-05 Hitachi Micro Comput Eng Ltd Microcomputer system
JPS59139428A (en) * 1982-12-28 1984-08-10 Fujitsu Ltd Direct memory access system
JPS59167761A (en) * 1983-03-14 1984-09-21 Hitachi Ltd Computer system
JPH0340868B2 (en) * 1983-03-14 1991-06-20
JPS63113653A (en) * 1986-10-30 1988-05-18 Hitachi Ltd Semiconductor memory controller

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