JPS5734263A - Simple multiprocessor system - Google Patents

Simple multiprocessor system

Info

Publication number
JPS5734263A
JPS5734263A JP10756880A JP10756880A JPS5734263A JP S5734263 A JPS5734263 A JP S5734263A JP 10756880 A JP10756880 A JP 10756880A JP 10756880 A JP10756880 A JP 10756880A JP S5734263 A JPS5734263 A JP S5734263A
Authority
JP
Japan
Prior art keywords
instruction
memory
cpu
arbitor
queuing state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10756880A
Other languages
Japanese (ja)
Inventor
Fujio Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP10756880A priority Critical patent/JPS5734263A/en
Publication of JPS5734263A publication Critical patent/JPS5734263A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Abstract

PURPOSE:To transmit data with high quality and to perform arithmetic processing with a software by constituting a multiprocessor by connecting plural CPUs without deteriorating practically processing capacity of a CPU. CONSTITUTION:When any microprocessor CPU outputs an address of a common memory MO to a address bus in an execution cycle of an instruction, a controlling circuit 5 recognizes an address of a memory MO, requires use of the memory MO to an arbitor 6 and set the CPU to a queuing state. Further, when use of the memory MO is permitted from the arbitor 6, the common bus is made to be operatable, and after a prescribed delay time, the queuing state is released to execute the instruction. After that, where access terminates, the bus MO is made to be not operatable, and a requirement to the arbitor 6 is withdrawn. In this execution circuit, only an execution cycle of an instruction becomes sometimes a queuing state, and in a read cycle of an instruction, a queuing state does not occur, thus a processing capacity of the CPU is not deteriorated practically.
JP10756880A 1980-08-04 1980-08-04 Simple multiprocessor system Pending JPS5734263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10756880A JPS5734263A (en) 1980-08-04 1980-08-04 Simple multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10756880A JPS5734263A (en) 1980-08-04 1980-08-04 Simple multiprocessor system

Publications (1)

Publication Number Publication Date
JPS5734263A true JPS5734263A (en) 1982-02-24

Family

ID=14462464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10756880A Pending JPS5734263A (en) 1980-08-04 1980-08-04 Simple multiprocessor system

Country Status (1)

Country Link
JP (1) JPS5734263A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178553A (en) * 1981-04-27 1982-11-02 Nec Corp Multiprocessor system
US6587932B2 (en) 1997-10-09 2003-07-01 Stmicroelectronics S.A. Processor and system for controlling shared access to a memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57178553A (en) * 1981-04-27 1982-11-02 Nec Corp Multiprocessor system
JPS6326907B2 (en) * 1981-04-27 1988-06-01 Nippon Denki Kk
US6587932B2 (en) 1997-10-09 2003-07-01 Stmicroelectronics S.A. Processor and system for controlling shared access to a memory

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