JPS54140841A - Memory control system of multiprocessor system - Google Patents

Memory control system of multiprocessor system

Info

Publication number
JPS54140841A
JPS54140841A JP4884778A JP4884778A JPS54140841A JP S54140841 A JPS54140841 A JP S54140841A JP 4884778 A JP4884778 A JP 4884778A JP 4884778 A JP4884778 A JP 4884778A JP S54140841 A JPS54140841 A JP S54140841A
Authority
JP
Japan
Prior art keywords
unit
processors
main memory
cash
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4884778A
Other languages
Japanese (ja)
Inventor
Masanobu Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4884778A priority Critical patent/JPS54140841A/en
Publication of JPS54140841A publication Critical patent/JPS54140841A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To make the content of a cash memory equal to that of the memory of a main memory unit, by providing a bus which transfers address information from the main memory unit to a central processor with the cash memory.
CONSTITUTION: This system consists of central processors 2 to 5 which have cash memories 12 to 15 stored with the data of main memory unit 1 block by block, main memory unit 1 to which access is made from processors 2 to 5, and two input-output data trnsfer controllers 6 and 7. When write requests are made from processors 2 to 5 to unit 1, write data, write addresses and machine numgers allotted to processors 2 to 5 are all sent out to unit 1 and then transferred from unit 1 to processors 2 to 5 via the bus, so that when the machine number from unit 1 disagrees with its own one, blocks on memories 12 to 15 indicated by the write addresses from unit 1 will be made ineffective.
COPYRIGHT: (C)1979,JPO&Japio
JP4884778A 1978-04-25 1978-04-25 Memory control system of multiprocessor system Pending JPS54140841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4884778A JPS54140841A (en) 1978-04-25 1978-04-25 Memory control system of multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4884778A JPS54140841A (en) 1978-04-25 1978-04-25 Memory control system of multiprocessor system

Publications (1)

Publication Number Publication Date
JPS54140841A true JPS54140841A (en) 1979-11-01

Family

ID=12814643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4884778A Pending JPS54140841A (en) 1978-04-25 1978-04-25 Memory control system of multiprocessor system

Country Status (1)

Country Link
JP (1) JPS54140841A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130877A (en) * 1980-03-19 1981-10-14 Hitachi Ltd Control system for burrer memory
JPH04328653A (en) * 1991-04-22 1992-11-17 Internatl Business Mach Corp <Ibm> Multiprocessor system and data transmitter therefor
JP2005148771A (en) * 2002-06-28 2005-06-09 Sun Microsyst Inc Mechanism for maintaining cache consistency in computer system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56130877A (en) * 1980-03-19 1981-10-14 Hitachi Ltd Control system for burrer memory
JPS622344B2 (en) * 1980-03-19 1987-01-19 Hitachi Seisakusho Kk
JPH04328653A (en) * 1991-04-22 1992-11-17 Internatl Business Mach Corp <Ibm> Multiprocessor system and data transmitter therefor
JP2005148771A (en) * 2002-06-28 2005-06-09 Sun Microsyst Inc Mechanism for maintaining cache consistency in computer system

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