JPS54140841A - Memory control system of multiprocessor system - Google Patents
Memory control system of multiprocessor systemInfo
- Publication number
- JPS54140841A JPS54140841A JP4884778A JP4884778A JPS54140841A JP S54140841 A JPS54140841 A JP S54140841A JP 4884778 A JP4884778 A JP 4884778A JP 4884778 A JP4884778 A JP 4884778A JP S54140841 A JPS54140841 A JP S54140841A
- Authority
- JP
- Japan
- Prior art keywords
- unit
- processors
- main memory
- cash
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To make the content of a cash memory equal to that of the memory of a main memory unit, by providing a bus which transfers address information from the main memory unit to a central processor with the cash memory.
CONSTITUTION: This system consists of central processors 2 to 5 which have cash memories 12 to 15 stored with the data of main memory unit 1 block by block, main memory unit 1 to which access is made from processors 2 to 5, and two input-output data trnsfer controllers 6 and 7. When write requests are made from processors 2 to 5 to unit 1, write data, write addresses and machine numgers allotted to processors 2 to 5 are all sent out to unit 1 and then transferred from unit 1 to processors 2 to 5 via the bus, so that when the machine number from unit 1 disagrees with its own one, blocks on memories 12 to 15 indicated by the write addresses from unit 1 will be made ineffective.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4884778A JPS54140841A (en) | 1978-04-25 | 1978-04-25 | Memory control system of multiprocessor system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4884778A JPS54140841A (en) | 1978-04-25 | 1978-04-25 | Memory control system of multiprocessor system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54140841A true JPS54140841A (en) | 1979-11-01 |
Family
ID=12814643
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4884778A Pending JPS54140841A (en) | 1978-04-25 | 1978-04-25 | Memory control system of multiprocessor system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54140841A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56130877A (en) * | 1980-03-19 | 1981-10-14 | Hitachi Ltd | Control system for burrer memory |
JPH04328653A (en) * | 1991-04-22 | 1992-11-17 | Internatl Business Mach Corp <Ibm> | Multiprocessor system and data transmitter therefor |
JP2005148771A (en) * | 2002-06-28 | 2005-06-09 | Sun Microsyst Inc | Mechanism for maintaining cache consistency in computer system |
-
1978
- 1978-04-25 JP JP4884778A patent/JPS54140841A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56130877A (en) * | 1980-03-19 | 1981-10-14 | Hitachi Ltd | Control system for burrer memory |
JPS622344B2 (en) * | 1980-03-19 | 1987-01-19 | Hitachi Seisakusho Kk | |
JPH04328653A (en) * | 1991-04-22 | 1992-11-17 | Internatl Business Mach Corp <Ibm> | Multiprocessor system and data transmitter therefor |
JP2005148771A (en) * | 2002-06-28 | 2005-06-09 | Sun Microsyst Inc | Mechanism for maintaining cache consistency in computer system |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS57105879A (en) | Control system for storage device | |
JPS5580164A (en) | Main memory constitution control system | |
JPS56123051A (en) | Data transfer system in master slave system | |
JPS54140841A (en) | Memory control system of multiprocessor system | |
ES416400A1 (en) | Data processing systems | |
JPS55108027A (en) | Processor system | |
JPS54122059A (en) | Inter-processor information transfer system | |
JPS5640391A (en) | Multiprocessor control system | |
JPS5561866A (en) | Memory designation system | |
JPS6478361A (en) | Data processing system | |
JPS5587220A (en) | Interface controller | |
JPS5786968A (en) | Doubled computer system | |
JPS5491028A (en) | Memory control system of multiprocessor system | |
JPS6476342A (en) | Information processing system | |
JPS55118164A (en) | Memory bank control system | |
JPS53132233A (en) | Memory access system | |
JPS57197661A (en) | Multiplex controlling system for file memory | |
JPS5578321A (en) | Data transfer control system | |
JPS5614364A (en) | Shared memory control system | |
JPS5724088A (en) | Buffer memory control system | |
JPS57152600A (en) | Duplicating system of memory device | |
JPS54134529A (en) | Information processing system | |
JPS5362939A (en) | Common information control system | |
JPS54122060A (en) | Inter-processor information transfer system | |
JPS56135260A (en) | Inter-processor information transfer system |