JPS55118164A - Memory bank control system - Google Patents
Memory bank control systemInfo
- Publication number
- JPS55118164A JPS55118164A JP2552779A JP2552779A JPS55118164A JP S55118164 A JPS55118164 A JP S55118164A JP 2552779 A JP2552779 A JP 2552779A JP 2552779 A JP2552779 A JP 2552779A JP S55118164 A JPS55118164 A JP S55118164A
- Authority
- JP
- Japan
- Prior art keywords
- memory bank
- adaptor
- bus
- memory
- bank
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To ensure the free selection of the memory bank in the system which gives switching to the memory bank at the read/write request time for the access control, by realizing the common bus for the memory bank selection signal in the form of the memory bank address.
CONSTITUTION: The bank address functions as common bus 8, and the CPU1 and I/O adaptor 3 hold the bank information each. Memory banks 4, 5 and 6 give the monitor to the bank address, and then deliver the data via the common data/ address bus when receiving the request to their own. With end of the access request of adaptor 3, the access request is sent out after obtaining the use permission of bus control adaptor 2 if the CPU requests the access. The transmission of the memory bank address is permitted only to the CPU or the I/O adaptor that has the use permission for the bus. Thus the free selection becomes possible to the different memory banks.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2552779A JPS55118164A (en) | 1979-03-07 | 1979-03-07 | Memory bank control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2552779A JPS55118164A (en) | 1979-03-07 | 1979-03-07 | Memory bank control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55118164A true JPS55118164A (en) | 1980-09-10 |
Family
ID=12168507
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2552779A Pending JPS55118164A (en) | 1979-03-07 | 1979-03-07 | Memory bank control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55118164A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6478337A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Control system for main memory access priority order |
-
1979
- 1979-03-07 JP JP2552779A patent/JPS55118164A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6478337A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Control system for main memory access priority order |
JPH0528855B2 (en) * | 1987-09-19 | 1993-04-27 | Fujitsu Ltd |
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