JPS56123051A - Data transfer system in master slave system - Google Patents

Data transfer system in master slave system

Info

Publication number
JPS56123051A
JPS56123051A JP2702780A JP2702780A JPS56123051A JP S56123051 A JPS56123051 A JP S56123051A JP 2702780 A JP2702780 A JP 2702780A JP 2702780 A JP2702780 A JP 2702780A JP S56123051 A JPS56123051 A JP S56123051A
Authority
JP
Japan
Prior art keywords
main memory
slave
data transfer
cpu
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2702780A
Other languages
Japanese (ja)
Other versions
JPS5835295B2 (en
Inventor
Kenichi Onishi
Minoru Nagao
Makoto Kawai
Masahiro Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP55027027A priority Critical patent/JPS5835295B2/en
Publication of JPS56123051A publication Critical patent/JPS56123051A/en
Publication of JPS5835295B2 publication Critical patent/JPS5835295B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To eliminate excessive busses, by causing the slave CPU to access the main memory by the main memory access instruction, which is read out from the main memory by the command from the master CPU, in the master slave system. CONSTITUTION:In case of data transfer between main memory 22 and internal memory 32 in the slave CPU, instructions including the main memory read instruction and the main memory write instruction for this data transfer stored in main memory 22 are read out to slave CPU21 by master CPU21. Slave CPU21 processes these instructions to access main memory 22 and executs data transfer between main memory 22 and internal memory 32. Consequently, even if the master CPU cannot access the internal memory of the slave CPU directly, the master CPU instructs data transfer between the internal memory of the slave CPU and the main memory without providing excessive address busses and data busses.
JP55027027A 1980-03-03 1980-03-03 Data transfer method in master-slave system Expired JPS5835295B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55027027A JPS5835295B2 (en) 1980-03-03 1980-03-03 Data transfer method in master-slave system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55027027A JPS5835295B2 (en) 1980-03-03 1980-03-03 Data transfer method in master-slave system

Publications (2)

Publication Number Publication Date
JPS56123051A true JPS56123051A (en) 1981-09-26
JPS5835295B2 JPS5835295B2 (en) 1983-08-02

Family

ID=12209584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55027027A Expired JPS5835295B2 (en) 1980-03-03 1980-03-03 Data transfer method in master-slave system

Country Status (1)

Country Link
JP (1) JPS5835295B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990133A (en) * 1982-05-21 1984-05-24 ピツトネイ・ボウズ・インコ−ポレ−テツド Direct memory access data transfer unit
JPS6118995A (en) * 1984-07-05 1986-01-27 カシオ計算機株式会社 Performance system
JPS61262955A (en) * 1985-05-17 1986-11-20 Fujitsu Ltd Buffer control system for communication controlling equipment
JPS63172361A (en) * 1987-01-12 1988-07-16 Hitachi Ltd Inter-processor communication system for multi-processor system
JPH01194055A (en) * 1988-01-29 1989-08-04 Hitachi Ltd Parallel computer
WO2002077848A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
WO2002077826A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
WO2002077845A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
WO2002077846A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
US6809734B2 (en) 2001-03-22 2004-10-26 Sony Computer Entertainment Inc. Resource dedication system and method for a computer architecture for broadband networks
US7024519B2 (en) 2002-05-06 2006-04-04 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US7231500B2 (en) 2001-03-22 2007-06-12 Sony Computer Entertainment Inc. External data interface in a computer architecture for broadband networks

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6231991A (en) * 1985-08-02 1987-02-10 アルプス電気株式会社 Dispersion type electric field light emitting element
JPS6269492A (en) * 1985-09-20 1987-03-30 アルプス電気株式会社 Thin film el display element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52142443A (en) * 1976-05-21 1977-11-28 Mitsubishi Electric Corp Microprogram write-in method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52142443A (en) * 1976-05-21 1977-11-28 Mitsubishi Electric Corp Microprogram write-in method

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990133A (en) * 1982-05-21 1984-05-24 ピツトネイ・ボウズ・インコ−ポレ−テツド Direct memory access data transfer unit
JPS6118995A (en) * 1984-07-05 1986-01-27 カシオ計算機株式会社 Performance system
JPS61262955A (en) * 1985-05-17 1986-11-20 Fujitsu Ltd Buffer control system for communication controlling equipment
JPS63172361A (en) * 1987-01-12 1988-07-16 Hitachi Ltd Inter-processor communication system for multi-processor system
JPH01194055A (en) * 1988-01-29 1989-08-04 Hitachi Ltd Parallel computer
JP2004252990A (en) * 2001-03-22 2004-09-09 Sony Computer Entertainment Inc Computer processor and processing device
US7093104B2 (en) 2001-03-22 2006-08-15 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
WO2002077845A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
WO2002077846A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
JP2002351850A (en) * 2001-03-22 2002-12-06 Sony Computer Entertainment Inc Data processing method on processor and data processing system
US6526491B2 (en) 2001-03-22 2003-02-25 Sony Corporation Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
JP2004078979A (en) * 2001-03-22 2004-03-11 Sony Computer Entertainment Inc Method and system for data processing in processor
WO2002077848A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
US6809734B2 (en) 2001-03-22 2004-10-26 Sony Computer Entertainment Inc. Resource dedication system and method for a computer architecture for broadband networks
US6826662B2 (en) 2001-03-22 2004-11-30 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
JP4489399B2 (en) * 2001-03-22 2010-06-23 株式会社ソニー・コンピュータエンタテインメント Data processing method and data processing system in processor
WO2002077826A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US7139882B2 (en) 2001-03-22 2006-11-21 Sony Computer Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US7231500B2 (en) 2001-03-22 2007-06-12 Sony Computer Entertainment Inc. External data interface in a computer architecture for broadband networks
US7233998B2 (en) 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
KR100840113B1 (en) * 2001-03-22 2008-06-20 가부시키가이샤 소니 컴퓨터 엔터테인먼트 Processing modules for computer architecture for broadband networks
US7457939B2 (en) 2001-03-22 2008-11-25 Sony Computer Entertainment Inc. Processing system with dedicated local memories and busy identification
US7720982B2 (en) 2001-03-22 2010-05-18 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
US7461207B2 (en) 2002-05-06 2008-12-02 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US7024519B2 (en) 2002-05-06 2006-04-04 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US7870340B2 (en) 2002-05-06 2011-01-11 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory

Also Published As

Publication number Publication date
JPS5835295B2 (en) 1983-08-02

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