JPS5614364A - Shared memory control system - Google Patents

Shared memory control system

Info

Publication number
JPS5614364A
JPS5614364A JP8823479A JP8823479A JPS5614364A JP S5614364 A JPS5614364 A JP S5614364A JP 8823479 A JP8823479 A JP 8823479A JP 8823479 A JP8823479 A JP 8823479A JP S5614364 A JPS5614364 A JP S5614364A
Authority
JP
Japan
Prior art keywords
cpu
shared memory
memory
write
shared
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8823479A
Other languages
Japanese (ja)
Inventor
Atomi Noguchi
Yoshihiro Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8823479A priority Critical patent/JPS5614364A/en
Publication of JPS5614364A publication Critical patent/JPS5614364A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To prevent the CPU of software development from giving operation interference to the CPU in on-line operation, by setting two kinds of property of the shared memory and by constituting the system so that two kinds of access method of the shared memory can be set by the CPU.
CONSTITUTION: The system is so constituted that plural CPUs 1, 2 and 3 can acess plural shared memories 4 and 5 through shared memory bus 6, and occupation control of bus 6 is performed by shared memory control unit 7. Access methods (a) and (b) are set to CPUs (A, B) for on-line and off-line respectively. Meanwhile, the A system and the B system are set to shared memories (C and D), and read/write from CPU A is made possible by memory C, and only write from CPU A is possible for memory D. Then read/write from CPU B where (b) is set is possible, thus preventing the CPU of software development from giving operation interference to the CPU in on-line operation.
COPYRIGHT: (C)1981,JPO&Japio
JP8823479A 1979-07-13 1979-07-13 Shared memory control system Pending JPS5614364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8823479A JPS5614364A (en) 1979-07-13 1979-07-13 Shared memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8823479A JPS5614364A (en) 1979-07-13 1979-07-13 Shared memory control system

Publications (1)

Publication Number Publication Date
JPS5614364A true JPS5614364A (en) 1981-02-12

Family

ID=13937167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8823479A Pending JPS5614364A (en) 1979-07-13 1979-07-13 Shared memory control system

Country Status (1)

Country Link
JP (1) JPS5614364A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0099125A2 (en) * 1982-07-15 1984-01-25 Hitachi, Ltd. Multicomputer system having dual common memories
JPH0395635A (en) * 1989-09-07 1991-04-22 Fujitsu Ltd Test system using common area

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0099125A2 (en) * 1982-07-15 1984-01-25 Hitachi, Ltd. Multicomputer system having dual common memories
JPH0395635A (en) * 1989-09-07 1991-04-22 Fujitsu Ltd Test system using common area

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