JPS55140953A - Abnormal operation detecting system for computer system - Google Patents

Abnormal operation detecting system for computer system

Info

Publication number
JPS55140953A
JPS55140953A JP4822479A JP4822479A JPS55140953A JP S55140953 A JPS55140953 A JP S55140953A JP 4822479 A JP4822479 A JP 4822479A JP 4822479 A JP4822479 A JP 4822479A JP S55140953 A JPS55140953 A JP S55140953A
Authority
JP
Japan
Prior art keywords
abnormal operation
program
cpu1
controlled unit
timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4822479A
Other languages
Japanese (ja)
Inventor
Toshio Tsuchiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP4822479A priority Critical patent/JPS55140953A/en
Publication of JPS55140953A publication Critical patent/JPS55140953A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To prevent the abnormal operation of the controlled unit which is caused by the abnormal operation of the program, by carrying out the process at the abnormal time by applying the interruption signal to the CPU from the timer at the time of the program abnormal operation during which the program is read out of the subcribed routine.
CONSTITUTION: Memory 2 storing the prescribed program and interface circuit 3 connected to the controlled unit are connected to CPU1 via address bus AB, data bus DB and control bus CB each, along with address decoder 4 connected via bus AB. Then the prescribed program stored in memory 2 is read out under the control of CPU1 to give the control to the controlled unit. In case the program is read out of the prescribed routine, the program of the abnormal operation is decided by decoder 4. And timer 5 connected to CPU1 is started to apply the interruption signal to CPU1 from timer 5. Thus the process is given by CPU1 when the abnormal operation is caused in order to prevent the abnormal operation of the controlled unit.
COPYRIGHT: (C)1980,JPO&Japio
JP4822479A 1979-04-19 1979-04-19 Abnormal operation detecting system for computer system Pending JPS55140953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4822479A JPS55140953A (en) 1979-04-19 1979-04-19 Abnormal operation detecting system for computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4822479A JPS55140953A (en) 1979-04-19 1979-04-19 Abnormal operation detecting system for computer system

Publications (1)

Publication Number Publication Date
JPS55140953A true JPS55140953A (en) 1980-11-04

Family

ID=12797440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4822479A Pending JPS55140953A (en) 1979-04-19 1979-04-19 Abnormal operation detecting system for computer system

Country Status (1)

Country Link
JP (1) JPS55140953A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57106926A (en) * 1980-12-24 1982-07-03 Nec Corp Program stole detecting system
JPS5894035U (en) * 1981-12-15 1983-06-25 松下電工株式会社 CPU operation monitoring system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119836A (en) * 1976-04-02 1977-10-07 Hitachi Ltd Calculator control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52119836A (en) * 1976-04-02 1977-10-07 Hitachi Ltd Calculator control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57106926A (en) * 1980-12-24 1982-07-03 Nec Corp Program stole detecting system
JPS5894035U (en) * 1981-12-15 1983-06-25 松下電工株式会社 CPU operation monitoring system

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