JPS54125930A - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS54125930A
JPS54125930A JP3286678A JP3286678A JPS54125930A JP S54125930 A JPS54125930 A JP S54125930A JP 3286678 A JP3286678 A JP 3286678A JP 3286678 A JP3286678 A JP 3286678A JP S54125930 A JPS54125930 A JP S54125930A
Authority
JP
Japan
Prior art keywords
memory
signal
transfer
access
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3286678A
Other languages
Japanese (ja)
Inventor
Masao Misumi
Yukimasa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3286678A priority Critical patent/JPS54125930A/en
Publication of JPS54125930A publication Critical patent/JPS54125930A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ensure the correct execution for both the information transfer and the CPU process between the volatile and nonvolatile memories of the multiple memory by inhibiting the access to the multiple memory unit of CPU for the period of transfer.
CONSTITUTION: With application of memory control signal 7, the transfer of information is executed all together between volatile memory 201 and nonvolatile memory 202 of plural units of multiple memory 200 constituting multiple memory unit 2. In this case, access inhibition signal 36 delivered in synchronization with driving signal 35 of generator circuit 32 is applied to READT signal circuit 312, and thus circuit 312 is controlled to deliver the NONREADY signal to indicate the access incapability to unit 2 (READY signal 90 delivered in case the access is possible) to be then applied to the READY terminal of CPU1. In other words, the transfer is executed between memory 201 and 202, and signal 36 is applied for the period during which the transfer is completed and memory 200 becomes steady in order to control circuit 312 of memory selection control circuit 31. Thus, the correct transfer of information is secured between memory 201 and 202.
COPYRIGHT: (C)1979,JPO&Japio
JP3286678A 1978-03-24 1978-03-24 Electronic computer Pending JPS54125930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3286678A JPS54125930A (en) 1978-03-24 1978-03-24 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3286678A JPS54125930A (en) 1978-03-24 1978-03-24 Electronic computer

Publications (1)

Publication Number Publication Date
JPS54125930A true JPS54125930A (en) 1979-09-29

Family

ID=12370769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3286678A Pending JPS54125930A (en) 1978-03-24 1978-03-24 Electronic computer

Country Status (1)

Country Link
JP (1) JPS54125930A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60262258A (en) * 1984-06-07 1985-12-25 Hitachi Ltd Memory circuit
JPH02163849A (en) * 1988-12-16 1990-06-25 Nec Corp Automatic memory back-up circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60262258A (en) * 1984-06-07 1985-12-25 Hitachi Ltd Memory circuit
JPH02163849A (en) * 1988-12-16 1990-06-25 Nec Corp Automatic memory back-up circuit

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