JPS5629755A - Testing device for logic circuit - Google Patents
Testing device for logic circuitInfo
- Publication number
- JPS5629755A JPS5629755A JP10478779A JP10478779A JPS5629755A JP S5629755 A JPS5629755 A JP S5629755A JP 10478779 A JP10478779 A JP 10478779A JP 10478779 A JP10478779 A JP 10478779A JP S5629755 A JPS5629755 A JP S5629755A
- Authority
- JP
- Japan
- Prior art keywords
- data
- supplied
- input mask
- input
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE: To reduce the time for production and transfer of the data and then reduce the memory capacity to store the data, by abbreviating the data supplied from the CPU only to the effective data by use of the input mask circuit and the effective data control circuit.
CONSTITUTION: In addition to the clock generating circuit 3, the input mask circuit 5 is provided to deliver the input mask signal in response to the input mask data supplied from outside. Furthermore, the effective data control circuit 7 is added to deliver the scan input data supplied from outside when the input mask signal is supplied ad then delivers the dummy input data when no input mask signal is supplied each. Thus the data supplied from the CPU can be abbreviated only to the effective data. As a result, the time can be reduced for both production and transfer of the data, at the same time reducing the memory capacity to store the data.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10478779A JPS5629755A (en) | 1979-08-16 | 1979-08-16 | Testing device for logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10478779A JPS5629755A (en) | 1979-08-16 | 1979-08-16 | Testing device for logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5629755A true JPS5629755A (en) | 1981-03-25 |
Family
ID=14390170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10478779A Pending JPS5629755A (en) | 1979-08-16 | 1979-08-16 | Testing device for logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5629755A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58205265A (en) * | 1982-05-26 | 1983-11-30 | Fujitsu Ltd | Scan loop check system |
JPS5921504A (en) * | 1982-07-10 | 1984-02-03 | デグツサ・アクチエンゲゼルシヤフト | Inorganic pigment and manufacture |
-
1979
- 1979-08-16 JP JP10478779A patent/JPS5629755A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58205265A (en) * | 1982-05-26 | 1983-11-30 | Fujitsu Ltd | Scan loop check system |
JPH0370811B2 (en) * | 1982-05-26 | 1991-11-11 | Fujitsu Ltd | |
JPS5921504A (en) * | 1982-07-10 | 1984-02-03 | デグツサ・アクチエンゲゼルシヤフト | Inorganic pigment and manufacture |
JPH0536369B2 (en) * | 1982-07-10 | 1993-05-28 | Degussa |
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