JPS5588140A - Address branch system of microprogram controller - Google Patents

Address branch system of microprogram controller

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Publication number
JPS5588140A
JPS5588140A JP16237078A JP16237078A JPS5588140A JP S5588140 A JPS5588140 A JP S5588140A JP 16237078 A JP16237078 A JP 16237078A JP 16237078 A JP16237078 A JP 16237078A JP S5588140 A JPS5588140 A JP S5588140A
Authority
JP
Japan
Prior art keywords
multiplexer
address
latch circuit
bit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16237078A
Other languages
Japanese (ja)
Inventor
Sunao Hirata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16237078A priority Critical patent/JPS5588140A/en
Publication of JPS5588140A publication Critical patent/JPS5588140A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the number of steps of instructions and to shorten the processing time by performing address-branch operation according to the state of a bit selected by a multiplexer when test and branch instructions are given.
CONSTITUTION: Arithmetic control part 1, work register 2 and latch circuit 3 are connected to data bus 6, and data of an arithmetic results, etc., are transferred via bus 6. Here, latch circuit 3 is temporarily stored with data on bus 6, and multiplexer 4 receives the contents of latch circuit 3 and selects a random bit under test conditions assigned by an instruction. When test and branch instructions are given, address branch operation is performed according to the state of the bit selected by multiplexer 4. Consequently, the assigned bit is tested and the address branch operation can be performed, so that the number of instruction steps can be reduced while the processing time is shortened.
COPYRIGHT: (C)1980,JPO&Japio
JP16237078A 1978-12-27 1978-12-27 Address branch system of microprogram controller Pending JPS5588140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16237078A JPS5588140A (en) 1978-12-27 1978-12-27 Address branch system of microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16237078A JPS5588140A (en) 1978-12-27 1978-12-27 Address branch system of microprogram controller

Publications (1)

Publication Number Publication Date
JPS5588140A true JPS5588140A (en) 1980-07-03

Family

ID=15753272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16237078A Pending JPS5588140A (en) 1978-12-27 1978-12-27 Address branch system of microprogram controller

Country Status (1)

Country Link
JP (1) JPS5588140A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837746A (en) * 1981-08-31 1983-03-05 Nippon Telegr & Teleph Corp <Ntt> Processor for condition discrimination
JPS6014338A (en) * 1983-06-30 1985-01-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Branch mechanism for computer system
JPS62109134A (en) * 1985-11-08 1987-05-20 Nec Corp Microprogram controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837746A (en) * 1981-08-31 1983-03-05 Nippon Telegr & Teleph Corp <Ntt> Processor for condition discrimination
JPS6014338A (en) * 1983-06-30 1985-01-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Branch mechanism for computer system
JPS62109134A (en) * 1985-11-08 1987-05-20 Nec Corp Microprogram controller

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