JPS56124960A - Memory access circuit - Google Patents

Memory access circuit

Info

Publication number
JPS56124960A
JPS56124960A JP2849480A JP2849480A JPS56124960A JP S56124960 A JPS56124960 A JP S56124960A JP 2849480 A JP2849480 A JP 2849480A JP 2849480 A JP2849480 A JP 2849480A JP S56124960 A JPS56124960 A JP S56124960A
Authority
JP
Japan
Prior art keywords
address
circuit
access
register
increase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2849480A
Other languages
Japanese (ja)
Inventor
Toru Nitta
Hiroshi Takashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2849480A priority Critical patent/JPS56124960A/en
Publication of JPS56124960A publication Critical patent/JPS56124960A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To reduce a burden for generating an address of access and prevent an increase of a circuit scale and an access time, in case of realizing a multi-access and a multiprogram, by adding a simple circuit by both the address register and the OR circuit. CONSTITUTION:When the processing equipment 1 executes its processing to the first object to be processed, the head address 3 is set in advance to the head address register 2 by the equipment 1. Subsequently, a logical address 4 for executing a program is sent to the OR circuit 5, it is brought to a logical operation with the head address 3 of the register 2 by the circuit 5, and it is output as a physical address 6. This physical address 6 is added to the memory device 7, it is accessed under control of a control bus signal 8, and a data of a data bus signal 9 is transferred. Also, to the second object to be processed, too, the head address is set to the register 2 in the same way, a program is executed, the burden for generating an address of access is reduced, and an increase of a circuit scale and an increase of an access time are prevented.
JP2849480A 1980-03-06 1980-03-06 Memory access circuit Pending JPS56124960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2849480A JPS56124960A (en) 1980-03-06 1980-03-06 Memory access circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2849480A JPS56124960A (en) 1980-03-06 1980-03-06 Memory access circuit

Publications (1)

Publication Number Publication Date
JPS56124960A true JPS56124960A (en) 1981-09-30

Family

ID=12250218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2849480A Pending JPS56124960A (en) 1980-03-06 1980-03-06 Memory access circuit

Country Status (1)

Country Link
JP (1) JPS56124960A (en)

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