JPS62109134A - Microprogram controller - Google Patents

Abstract

PURPOSE:To obtain a microinstruction control circuit that has branching function with a short instruction word length and a fast executing time, by extracting the prescribed data out of the latched parameter group to apply a mask to an extracted parameter and defining the data obtained from masking as an address of the branching destination. CONSTITUTION:A multi-way branch register 200 is connected to a data bus 106 and holds the whole or a part of the contents of the bus 106 when a latch signal WRMBR is produced. A multiplexer 201 selects and delivers the contents MBR of the register 200 according to the value of a selection field (sel) of a multi-branch microinstruction. A multi-branch address generator 202 produces the output of the multiplexer 201 and the address of the branching destination according to a mask field 'mask' and a base field 'base' of the multi-branch microinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J] The present invention relates to a text information processing device that entirely employs a microprogram control system, and more particularly to a microprogram branch control circuit.

[Conventional technology]

Conventional program counter? In an information processing device that fully employs the microprogram control method used, a type of microinstruction called a branch microinstruction is used to completely change the control flow (sequence). The branch microinstruction accomplishes all of the sequence changes by replacing all or part of the current contents of the program counter with the contents of the branch target address field that the branch microinstruction has as an operand. At this time, a branch microinstruction that has a condition field as another operand is called a conditional branch microinstruction, and branches only if the specified condition matches the current state in the information processing block. It is something that performs an action. ! Figure 2 shows the general format of a conditional branch microinstruction.

FIG. 3 shows a block diagram of an information processing device that completely adopts the conventional microprogram control method. data bus 10
6, the register file 110 and the arithmetic processing unit 107 are connected, and the register file 11
Arithmetic or logical operations can be performed on data stored in 0.

The microprogram stored in the microinstruction memory 101 is accessed by the address indicated by the address register 100, and the corresponding microinstruction is latched in the instruction latch 102 and then transferred to the instruction decoder 104.
The information is analyzed by the following, and a control issue (micro order) for the control possibility within the information processing device is generated. Thus, when a conditional branch microinstruction is detected by the instruction taker 104, the microorder MJM
P is issued. In the branch condition determination circuit 108, MJM
When P full fi4 is issued, the contents of the condition field N■BoD in the branch microinstruction are compared with the status signal S'I''ATUB indicating the status of the arithmetic processing unit, and it is determined whether the branch condition is satisfied. If the condition is satisfied, a match signal LDJMPk is generated.

The address register 100 is set to address register 1 when the Ll) JMP signal is inactive.
%MA'i+1 increment of 00 103
By loading gk, the address contents are sequentially incremented by 1, and the microinstructions are sequentially accessed. - When the LDJMP signal is generated, the entire branch operation is performed by loading the address of the branch destination determined by the address field of the branch micro FR + labor into the output care address register 100 of the branch address generation 1109. .

A branch function that changes the branch destination address according to a single parameter that changes during the execution of a microprogram is called a multi-way branch function.

Now, there is a possibility that the parameter N changes up to Q-n,
When the parameter is 0, it is a set of microinstructions 10
When the parameter N is 1, the procedure is 10, and when the parameter N is n, the procedure is 10.
(Consider an example of an application that does not require execution.

In an information processing apparatus that employs all conventional microprogram control devices, processing using a plurality of microinstructions as described below is required in order to realize the multi-branching system.

■Check whether N is 0. ■If it is 0, branch to procedure 0. ■If the result is 0, proceed to procedure 0. ■ If the result is 0, branch to 10 or 1. In the above process of branching to n, steps ■, ■, and ■ are subtraction operations? Therefore, the arithmetic and logic unit t107 is used, and in steps ①, ②, and ②, is the operation result in the arithmetic and logic unit 107 0? Conditional branching micro-life to judge!
It is used for.

Furthermore, when the parameter IN exceeds nf, the following processing is additionally required in order to detect this as an entirely invalid first shift.

■N - n 7; Calculate z ■If the result is positive, branch to the error handling procedure As explained above, in order to change the procedure to be executed by changing one parameter, at least the procedure Since it is used for only a few arithmetic microinstructions and conditional branch microinstructions, it has the disadvantage that the capacity of the microprogram increases and the time required to branch to each procedure increases on average.

Furthermore, although all branch functions are essentially realized, all M arithmetic operations are performed by the register file 110,
The data bus 106 has all the drawbacks of having to occupy hardware resources involved in data manipulation, such as the arithmetic and logic unit 107.

Procedures that are executed according to the parameter values It is clear for the example of code processing in arithmetic.

Beu is a numerical representation system that is expressed as a binary number from 0 to 9 (il-4 bits oooo to 1001).

Each 4 pits is called a digit, and 1 byte (8
2-digit Bea'l is stored in the bit) data. In particular, this type of CD may be distinguished as a packed BCL), an unpacked BUI) in which each 1-byte data stores a single digit beL), and a typical unpacked BUI) as shown in Figure 4. format. Byte data Bn containing the most significant digit (MSD) (N or 848 if the length of the digit appearing in the numerical value purple is an odd number) The next byte data Bn+1 containing the byte data Bn containing J (
If the length of digits representing a numerical value is an even number, the upper digits of (/) are used as sign digits to indicate whether the decimal number represented by the digits representing each numerical value is positive or negative. Specify. On the other hand, digits other than the code digits are called number 1 direct digits.

The code digit assigns a decimal code to the value, but the most frequently used values are values that are incorrect for the number 1 key, that is, 1010 to 1111. The contents of the code digits and the corresponding relationship between the codes are shown below.

Code digit Code 1010 Positive 1011 Negative 1100 Positive 1101 Koma 1110 Positive 1111 Positive The basic concept of the above coding system is that if the value of the least significant bit (LSB) of the code digit is 0, it is positive, and if it is 1, it is negative. , as an exception, only when the code digit is 11111) is positive.

Furthermore, the code digit is in an area other than the above, ie, ooo.

-1001 (these days are the correct range for numerical digits, and the imperial range of numerical digits and the range of code digits are mutually exclusive), there is an error in the representation method of the decimal number as a whole. Must be inspected.

Procedure pr that handles positive numbers with 8 answers of sign digits
oc-plu\Glossija pr that handles negative numbers.

A multi-branching function for branching to the procedure proc-error to be processed when an error 'r in the expression method for c-minu is detected and performing each process is described as follows.

if 5IGN(1001b then proc-
error; /* Check validity of code digit */ if 8IGN=XXXOb then proc-p
lus; / *Basic check for positive numbers Ice/ if 5IGN=1111b then proc-p
lus; / *Exception check for positive numbers */ proc-minus: ...... ...... /* Processing of positive numbers ×/proc-error: ...... Show contents.

When expressed in a microprogram with a high-level language-like description as described above, the number of steps is several times larger, so the capacity of the microprogram and each 70 steps (proc
-errorlproc-plus and proc-m
The average number of execution steps until the start of execution of i nus) becomes longer.

Is the code digit processing described above a k3cD operation? Since this is a preprocessing that is always executed when performing a BCD operation, the execution time of this process is always reflected in the execution time of the BCD operation. BCD6
When it comes to the disappointing performance of arithmetic, the execution time of code digit processing becomes dominant in terms of performance.

Furthermore, it is necessary to check the validity of numerical digits before starting the calculation. As mentioned above, the numerical digits 0000-1001 are correct, and the digits 1010-1111 must be detected as errors. Numerical digits are stored divided into the upper or lower 4 bits of each byte data, and the validity check of each digit is performed by checking whether it is an even numbered digit or an odd numbered digit. digit alignment is required.

Like code digit processing, preprocessing is always executed when IL and BCD calculations are performed9, and it can be said that it has a great influence on the overall calculation time.

[Problem to be solved by the invention J] In view of the drawbacks of the conventional example, the problem is that when a long parameter, a variable length parameter, or a number parameter is compressed into one parameter, It is an object of the present invention to provide a microinstruction control circuit having a short instruction word length and fast execution time when branching to a plurality of addresses depending on one parameter.

[Means for solving the problem J In the microprogram control fclt, a latch whose value is set by the execution of a microinstruction 1c, means for extracting the data held in the latch, and data extracted by the extracting means The branch address is masked and determined by the data.

[Operation/Principle of the Invention J] The present invention latches all parameter groups in advance, extracts sufficient data from the latched parameter group, masks the extracted parameters, and masks the data obtained by masking the branch destination address. By doing so, the actual Ic of the parameter can be shortened, and by masking, it is possible to select the bit '1 that is involved in the branching function from among the divided parameters.

〔Example〕

The configuration and operation of the invention will be described in detail below with reference to the drawings.

Fig. 1 shows the complete explanation of the present invention. FIG.

The address register 203 indicates which microinstruction should be added next when the execution of the sequential micro7g generated by the incrementer 103 progresses. Stored address, when executing an unconditional or conditional branch microinstruction 1, 1) Batch destination address generated by the branch address generator 109 according to the JMP signal, and when executing a multi-branch microinstruction LL) MLSi - multiway blatch address generator 2 by signal
This register latches the address of the latch destination generated by 02. Multiway blatch register 2υ0
is connected to the data bus 106 and receives the latch signal WRM
B) A latch that holds the entire contents of data bus 106 or a portion thereof when t occurs.

Multiplexer 201fl, multiway blatch
The contents of the register 200 are selectively output according to the selection field 5elD value of the MBR multi-branch microinstruction. Multi-way blur address generator 202U, output of multiplexer 201, mask field mask and base field base of multi-branch microinstruction
This is a circuit that generates a branch destination address determined by K steps. The instruction decoder 204 generates micro-orders such as a signal WRMB which indicates that the transfer micro-instruction specifies transfer to the multi-way blatch register 200 and a signal LIJMB which indicates that a multi-branch micro-instruction is to be executed. It is a means.

FIG. 5 shows an example of a multi-branch microinstruction.

Op is a field that indicates the operation code of the multi-branch microinstruction, sel is a field that selects data to be connected to the multiway blatch address generator 202 based on the contents of the multiway blatch register 200, and m35 is a field that indicates the operation code of the multi-branch microinstruction. Base is a field that adds bit-corresponding validity r to the field of the selected multiway blatch register 200, and base is a field that is used as a base address generator for the branch destination address.

The specific operation of this embodiment will be explained below.

The M b-bit parameters Nm''''c free data params are latched into the multi-way latch register 200 by the latch signal W generated by the instruction decoder 204 during execution of the transfer microinstruction. When the multi-branch micro-instruction is latched into the instruction latch 102, the instruction decoder 103 outputs the micro-order LL) MB.
Ri is generated. The multiplexer 203 outputs the parameter N5elp specified by the selection field 5eILL of the multi-branch microinstruction, and outputs the mask field ma.
Take sk and mBJi, add two 07, and generate all the lower b1z bits of the branch destination address.

The multi-branch microinstruction detection signal LL) MBK is generated, the lower b+zu of the address register 202 is the output of the multi-way blur address generator 202, and the upper side is the base field bas of the multi-branch microinstruction.
By latching e, a new branch destination address is determined. This operation is shown in FIG.

The above specific operation is performed when the branch destination address knew-ad
rs, it can be expressed as the following equation.

new-adrs=base”12 b+-Z))
(paraTls(Seandmask) + (
2^z); Here params(sel) is the selection field se
b bit data of the friend multiway blatch register 200 selected by l.

FIG. 7 shows a more specific embodiment of the invention. In this specific example, the 8-bit parameter ? It is divided into two parts and can be multi-branched up to 16 ways according to the selected parameters.

The multi-branch microinstruction in this embodiment has a seven format format, as shown in FIG. sel, 4-bit mask field mas
13 bits of k and 1 bit (dly) which are not involved in the present invention are left alone.

It is assumed that this multi-branch microinstruction is written as follows.

MJMPO (Ei”, Utanken); MJMPI (Sen” Kun Jren); MJMPO command has selection field 5elf,
The JMPl command is the same except that the selection field is set to sel 1kl. All the starting addresses of the multi-branch destinations of the 16fil type are written on the same page, but the following restrictions are imposed.

MA % (2△8)=adrs% (2△8 pieces... limit 1adrs mod (2△5)=0...
......Restriction 2 Here, - is an integer division operator.

These restrictions apply if the first address of the multi-branch destination is at the beginning of the 32-word boundary and the current address (the address where the multi-branch microinstruction is written) is
It specifies that the upper 8 bits are the same address. These conditions do not pose any disadvantage to the microprogram if the logical address space of the microinstruction memory 101 is sufficiently large.

adrs (!: base address feel)”ba
The relationship of se is given by the following equation.

base=(adrs%(2△5))mod(2
△Illusion: The address space of the microinstruction memory 101 is 1
The address MAO is given in 6 bits and the address register 304 stores the microinstruction to be executed next.
-15 indicates.

The address register 304 contains an LDMB signal pressure signal indicating that a multi-branch microinstruction has been decoded.
A8-15', the next 3 bits contain the 1st shift of the base address field base of the multi-branch microinstruction, and the next 4 bits contain the 2-manual ANL) output of gates 310-313? , the lowest pit is connected to the logic (l latched, 8-bit register 300h, lowest 8 vias of the f-bit bus 106), and when the latch signal WkLiViB9 becomes active, the lowest bit of the data bus 106 is connected. Latch all lower 8 bits in 1st shift. 4-bit multiplexer 30
1 is the output of the lower 4 of the 8-bit register 300 when the selection field sel of the multi-branch i-microcoordination is O.
Bit? , when the selection signal sel is 1, all upper 4 bits of the 8-bit register are output.

4 corresponding to the output of the 4-bit multiplexer 301 and the mask field mask of the multi-branch microinstruction.
Bit data is 2-man power ANl) Gate 31
Connected to 0-313, logical score? Supply to the middle 4 bits of the address register.

Next, the operation of the non-embodiment will be explained using an example of the code processing described above BC1). Now, by executing the transfer microinstruction, the 8-bit register 300 is set to 0111100b (
(JBF”h) is set.

Multi-branch microinstruction MJMi'1 at address 0100
When (prOc-base, llll1b); is about to be executed, the microorder LIJMB becomes active. At this time, each field of the multi-branch microinstruction is
It is set as if it were dark.

sel......1b base......001b mask......1lllb The current value of the address register 304 is oooo.

Since it is 00100000000b, the upper 8 bits of the address register 304 are newly set to UOOOOOUOl.
b, the next 3 bits are set to the base value ooib, and the next 4 bits are set to the outputs of the two-manufactured ANIJ310 to 313. Since the sel signal is 1, the upper 4 bits of the 8-bit register 300 are set. 1m1111M') AND of mask for data 1011b? 101 taken
1b should be set. The least significant bit of the address register is always set to O.

As a result of the above operations, the address register 304 becomes oo
It is set to ooooolooolioiiob, that is, address 0136.

Similarly, the upper 4 bits of data n of the 8-bit destination register
Depending on the value of the multi-branch microinstruction MJMP1 (pro
c-base, 111 l b); execution result,
The address moves as follows.

n (binary) 2-2 ward (hexadecimal) 1110
013C 1111013E These branch destination addresses include proc-plug for processing positive numbers, proc-minus for processing negative numbers, and error processing f9 f 'rT as shown below.
Branch microinstruction JM to fx upproc-error
)'(proc-plus);, JMP (proc-
minus) ;Process JMP (proc-erro
r) is described, and after the execution of the multi-branched microalloy is completed, the control transitions to one of the 10 stages.

FIG. 9 shows the location-to-run relationship of these 10 multi-branch microinstructions.

70 Shijiya Processing Address proc-plus Positive number 0134,0138,0
130,013Hproc -minus negative number
0136,013Aproc-error Error 0120,0122,0124,0126,0128
゜012A, 0120, 01 seat, 0130, 0132 In the above operation example, after the 0136a section control is transferred, JMP
(proc-minus) ;Instruction -? By T, control is transferred to the negative number processing procedure described in proc-minus.

Similarly, the upper 4 bits 11 of the 8-bit register 300
If 10b is set, go to proc-plus via address 013C and process positive numbers? ,0010
If b is set, it is possible to move to proc-error via address 0128 and start a processing procedure for the error.

Next, another operation in this conventional example will be explained.

In this example of operation, it is assumed that the value of the 8-bit status register 400 is set in the 8-bit register 400 for the execution of a transfer microinstruction, as shown in FIG. Each bit of status register 400 is
VC three fields STO (3 bits) as shown below
, 5TI (2 bits) and Sr1 (1 bit), and are respectively located at bits o-2, bits 5-6 and bit 7 of the status register.

Bits 3 and 4 of status register 400 are undefined but missing.

Use the following commands to check each field.

Field Multi-branch microinstruction
S'l”o MJMPO(adrsO,01l
lb); 0, 2.4, 6, 8. O.A.

People, shout (+adrsO) STI MJME'1 (adrsl, 0] 10b
); 4. s, oe, tm (+adrsl) Sr1 MJMPI (adrs2, 1000b)
; 0,8 (+adrs2) For example, ST1 field? When checking, if the content of S1'1 is oob, control is transferred to address 4, if it is Olb, it is address 8, if it is 10b, it is OC address, and if it is address 11, it is transferred to OE belt (each pace address adr81k blade). be able to.

In the above-described uninvented embodiment, the 8-bit parameter is divided into two, and 2.4.8.16 ways can be selected from a maximum of 16 ways, but the length of the multiway blatch register 200, By increasing the length of the parameter selection field Sal of the multi-branch micro-instruction, it is possible to multiplex all of the longer parameters and provide all multi-branch micro-instructions with a high degree of multiplicity using short-length micro instructions. .

[Effects of the Invention] As has been explained above, by using the present invention, in a microprogram that requires changing processing depending on the contents of a parameter, all branching operations can be performed at high speed depending on the length of the parameter. Microinstructions with short instruction word length and high versatility? can be provided.

[Brief explanation of drawings]

Fig. 1 is a drawing showing a simple example of the present invention, Fig. 2 is a drawing showing the general format of conditional microinstructions, and Fig. 3 is an information processing system using a conventional micro-Sumigram control device. A drawing showing an example of a spoon, Figure 4 is back 1-B
Figure 5 is a diagram showing the general format of CH, Figure 5 is a diagram showing the general format of multi-branch micro instructions, Figure 6 is a diagram fully explaining the addressing method for multi-branch micro instructions, and Figure 7 is a diagram showing the present invention. Figure 8 is a diagram showing the concrete format of multi-branch microinstructions, Figure 91 is a diagram showing the location relationship of procedures in BCD code processing, FIG. 10 is a diagram showing the structure of the status register in another embodiment +9Il of the present invention. 100...address register, 101...microinstruction memory, 102...instruction latch, 103...
Incrementer, 104... Instruction coder, 105...
...Status generator, 106...Data bus, 1
07... Arithmetic logic unit, 108... Planner No. 18 generator, 109... Branch address generator, 1
DESCRIPTION OF SYMBOLS 10... Register file, 200... Multiway blatch register, 201... Multiplexer, 202... Multiway blatch address generator, 203... Address register, 204...
Instruction decoder, 300...8-bit latch, 301
...4-bit multiplexer, 302...Multiway blatch address generator, 303...16
Bit address register, 310-313...2
Human power ANL), 400... 8-bit status register agent Uchihara, patent attorney. OF Life θ Ichiruto tripped Figure 5 (Conventional #s) Part tail moth
High 1-Olα) Makishi level 1 length f phase hide Bτ High day gap
Hi/-0 (t non is (
Screen Q Off Dingji 13rf! #A of E

Claims (1)

[Claims] means for extracting at least part of the data from data held in a latch whose value is set by execution of a microinstruction; and means for selectively masking the data extracted by the extraction means with the microinstruction; A microprogram control device characterized in that all or part of an address is determined by the masked data.