JP2587407B2 - Micro program controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus employing a microprogram control method, and more particularly to a microprogram branch control circuit.

[Conventional technology]

2. Description of the Related Art Conventionally, in an information processing apparatus employing a microprogram control method using a program counter, a type of microinstruction called a branch microinstruction is used to change a control flow (sequence). In the case of a branch microinstruction, the sequence is changed by replacing all or a part of the current contents of the program counter with the contents of a branch destination address field that the branch microinstruction has as an operand. At this time, a branch microinstruction having a condition field as another operand is called a conditional branch microinstruction, and a branch operation is performed only when a specified condition matches the current state in the information processing device. Is performed. FIG. 2 shows the general format of a conditional branch microinstruction.

FIG. 3 shows a block diagram of an information processing apparatus employing a conventional microprogram control method. Data bus 10
6 has a register file 110 and an arithmetic processing unit
107 is connected, and can perform arithmetic or logical operation on the data stored in the register file 110.

The microprogram stored in the microinstruction memory 101 is accessed by the address specified by the address register 100, and after the corresponding microinstruction is once latched in the instruction latch 102, the microprogram is analyzed by the instruction degoder 104, whereby the information processing is performed. A control signal (micro order) for a control point in the device is generated. Thus, when the instruction decoder 104 detects a conditional branch microinstruction, a microorder MJMP is issued.
When detecting the MJMP, the branch condition determination circuit 108 compares the content of the condition field MCOD in the branch microinstruction with the status signal STATUS indicating the state of the arithmetic operation device, and determines whether the branch condition is satisfied. If so, a coincidence signal LDJMP is generated.

The address register 100 stores the contents MA of the address register 100 when the LDJMP signal is inactive.
Is incremented by one, the contents of the address are sequentially incremented by one, and micro-instructions are sequentially accessed. On the other hand, when the LDJMP occurs, the branch operation is performed by loading the output of the branch address generator 109 for generating the address of the branch destination determined by the address field of the branch microinstruction into the address register 100.

A branch function that changes a branch destination address in accordance with a single parameter that changes during the execution of a microprogram is called a multi-branch (multi-way branch) function.

Now, there is a possibility that the parameter N changes from 0 to n. When the parameter N is 0, the procedure (procedure) 0 which is a set of microinstructions is set. When the parameter N is 1, the procedure 1 is set. When N is n, consider an application example in which procedure n is executed.

In an information processing apparatus employing a conventional microprogram controller, in order to realize the multi-branch function,
Processing by a plurality of microinstructions as shown below is required.

Check whether N is 0. If 0, branch to procedure 0. Operate N-1. If result is 0, branch to procedure 1. Operate N-n. If result is 0, branch to procedure n. In the above, the arithmetic logic unit 107 is used because the step and the step involve a subtraction operation, and the conditional branch microinstruction for determining whether the operation result in the arithmetic logic unit 107 is 0 is used in the step and the step.

Further, when the parameter N exceeds n, in order to detect this as an invalid value, the following processing is additionally required.

Calculate N−n If the result is positive, branch to the procedure for error processing. As described above, in order to change the procedure to be executed according to the value of the parameter, at least the number of computation micro-instructions equal to the number of procedures, The use of conditional branch microinstructions has the disadvantage that the capacity of the microprogram is increased and the time required to branch to each procedure is increased on average.

In addition, the register file 110,
It has the disadvantage that it must occupy the hardware resources involved in data operations, such as data bus 106 and arithmetic logic unit 107.

As a process that needs to change the procedure to be executed depending on the value of the parameter, there is an application in which the procedure specifies the execution function as a command or status.
Here, a description will be given of an example of a code process in a binary coded decimal (BCD) arithmetic operation.

BCD is a 4-bit binary number from 0000 to 100 for values from 0 to 9.
It is a numerical representation system expressed by 1. Each 4 bits is called a digit (digit), and two bytes of BCD are stored in one byte (8 bits) of data. In particular, such BCDs are packed
The BCD may be distinguished from an unpacked BCD in which each one-byte data stores a one-digit BCD.

FIG. 4 shows a general format of an unpacked BCD. Byte data Bn including the most significant digit (MSD)
(If the length of the digit representing the number is odd) or
Byte data Bn following byte data Bn including MSD +
1 (when the length of the digit representing the numerical value is an even number, the upper digit specifies whether the decimal number represented by the example of the digit representing each numerical value is positive or negative as a sign digit On the other hand, digits other than the sign digit are called numerical digits.

The sign digit represents the sign of the decimal number by its value,
The most frequently used value is a value that is incorrect as a numerical value, that is, 1010 to 1111. A representative example of the correspondence between the contents of the sign digits and the sign is shown below. Sign Digit Code 1010 Positive 1011 Negative 1100 Positive 1101 Negative 1110 Positive 1111 Positive The basic concept of the coding system is that if the value of the least significant bit (LSB) of the sign digit is 0, it is positive if it is 1 and negative if it is 1. As an exception, only when the sign digit is 1111, it indicates positive.

Furthermore, the sign digit is a value other than the above, that is,
(These values are in the correct range for numeric digits, and the range of numeric digits and the range of sign digits are disjoint.) Must.

Procedure pr that handles positive numbers depending on the contents of the sign digit
oc-plus, procedure proc-minus that handles negative numbers, procedure that is processed when an error in the expression method is detected
The multi-branch function for branching to proc-error and performing each processing is described as follows.

Here, SIGN indicates the contents of the sign digit. When the high-level language-like description as described above is expressed by a microprogram, the number of steps is expanded to several times, so that the capacity of the microprogram and each procedure (proc-error, pro
The average number of execution steps before starting execution of c-plus and proc-minus) will be longer.

Since the above-described processing of the code digit is a pre-processing that is always performed when performing the BCD calculation, the execution time of this processing is always reflected in the execution time of the BCD calculation. When high performance is required for the BCD operation, the execution time for processing the code digit becomes dominant over the performance.

Further, regarding the numerical digits, it is necessary to check the validity of the numerical digits before starting the operation. As mentioned above, the correct value for the numeric digits is 0000-101,
Errors must be detected from 10 to 1111. Numerical digits are stored by being divided into the upper or lower 4 bits of each byte data. Therefore, the validity check of each digit depends on whether it is an even-numbered digit or an odd-numbered digit. Will be needed.

Similar to the processing of the sign digit, it is a pre-processing that is always executed when the BCD operation is performed, and can be said to have a large influence on the entire operation time.

[Problems to be solved by the invention]

The present invention has been made in view of the above-described drawbacks of the conventional example, and has been described in connection with a long parameter, a variable-length parameter, or a plurality of addresses when a plurality of parameters are compressed in one parameter. It is another object of the present invention to provide a microinstruction control circuit having a short instruction word length and a branching function with a fast execution time.

[Means for solving the problem]

According to the present invention, a latch connected to a data bus and holding parameter information on the data bus by execution of a transfer microinstruction, and extraction for extracting continuous predetermined bit string information from the parameter information held in the latch Means for selectively masking the data extracted by the extracting means with a branch microinstruction, and a microprogram in which all or a part of the branch destination address is determined by directly using the masked data. A control device is obtained.

[Action and principle of the invention]

According to the present invention, a parameter group is latched in advance, predetermined data is extracted from the latched parameter group, a mask is applied to the extracted parameter, and data obtained by masking is used as an address of a branch destination. Are reduced in length, and bits related to the branch function can be selected from the divided parameters by masking.

〔Example〕

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the present invention. The address register 203 is an address that stores a microinstruction to be executed next when the microprogram is sequentially executed by the incrementer 103,
When executing an unconditional or conditional branch microinstruction
This register latches the branch destination address generated by the branch address generator 109 by the LDJMP signal and the branch destination address generated by the multi-way branch address generator 202 by the LDMBR signal when executing a multi-branch microinstruction. . The multiway branch register 200 is connected to the data bus 106 and
This latch holds the contents of the data bus 106 or a part of the contents when the WRMBR occurs. Multiplexer 20
1 is the content MBR of the multiway branch register 200
According to the value of the selection field sel of the multi-branch microinstruction. The multiway branch address generator 202 is a circuit that generates a branch destination address determined by the output of the multiplexer 201, the mask field mask of the multi-branch microinstruction, and the base field base. The instruction decoder 204 generates a micro order such as a signal WRMBR indicating that the transfer microinstruction has designated transfer to the multiway branch register 200 and a signal LDMBR indicating that the multibranch microinstruction is to be executed. is there.

FIG. 5 shows an example of a multi-branch microinstruction. op is a field indicating the operation code of the multi-branch microinstruction, and sel is a multi-way branch address generator 202 based on the contents of the multi-way branch register 200.
A field for selecting the data to be connected to, the mask is the multi-way branch register 20 selected by sel
A field for specifying the validity of the bit correspondence for the field of 0, and base is a field for specifying the base address of the branch destination address.

 Hereinafter, a specific operation of the present embodiment will be described.

Data pa consisting of M b-bit parameters Nm
When the rams executes the transfer microinstruction, the instruction decoder 204
Is latched in the multi-way branch register 200 by the latch signal WRMBR generated. When the multi-branch microinstruction is latched in the instruction latch 102, the instruction decoder 2
04 generates micro-order LDMBR. Multiplexer 2
01 outputs the parameter Nsel specified by the selection field sel of the multi-branch microinstruction, ANDs it with the mask field mask and adds z zeros to generate the lower b + z bits of the branch destination address I do.

When the multi-branch microinstruction detection signal LDBMR occurs,
The lower b + z of the address register 203 is a multi-way
The new branch destination address is determined by latching the output of the branch address generator 202 and the base field base of the multi-branch microinstruction on the upper side. This operation is shown in FIG.

The specific operation described above is to change the branch destination address to new-adrs
Then, it can be expressed as the following equation.

^{new-adrs = base * (2} ∧ (b + z)) + (params (sel) and mask) * (2 ∧ z); wherein params (sel), the multiway branch register selected by the selection field sel 200 b
It is bit data.

FIG. 7 is a diagram showing a more specific embodiment of the present invention. In this specific embodiment, an 8-bit parameter is divided into two, and a maximum of 16 ways of multi-branch can be performed according to the selected parameter. The format of the multi-branch microinstruction in this embodiment is a 4-bit operation code field op, as shown in FIG.
3-bit base address field base, 1-bit selection field sel, 4-bit mask field mask, and 1-bit (dly) 1 not related to the present invention
Consists of 3 bits.

This multi-branch microinstruction shall be described as follows.

MJMP0 (adrs, mask); MJMP1 (adrs, mask); The MJMP0 instruction is common except that the selection field sel is set to 0, and the MJMP1 instruction is set except that the selection field sel is set to 1. adrs
Describes the start addresses of 16 types of multi-branch destinations, but is restricted as follows.

^{MA% (2 ∧ 8) =} adrs% (2 ∧ 8) ... limit ^{1 adrs mod (2 ∧ 5)} = 0 ... limit 2 where% is an operator indicating a integer division.

These restrictions are based on the fact that the start address of the multi-branch destination is at the beginning of the 32-word boundary, and the current address (the address where the multi-branch microinstruction is described) is
The upper 8 bits specify that the addresses are the same. These conditions are not a disadvantage for the microprogram if the logical address space of the microinstruction memory 101 is sufficiently large.

The relationship between adrs and base address field base is
It is given by the following equation.

^{base = (adrs% (2 ∧} 5)) mod (2 ∧ 3); the address space of the micro-instruction memory 101 is given by 16 bits, stores the microinstruction to be executed address register 304 is then Addresses MA0-15 are specified.

The address register 303 stores the most significant 8 bits by the LDMBR signal indicating that the multi-branch microinstruction has been decoded.
The upper 8 bits of the address register MA8-15
, The value of the base address field base of the multi-branch microinstruction in the next three bits, the output of the two-input AND gates 310 to 313 in the next four bits, and logical 0 in the least significant bit. . The 8-bit register 300 stores data
Connected to the least significant 8 bits of the bus 106, the latch signal WRMBR
Latches the value of the least significant 8 bits of the data bus 106 when is activated. 4-bit multiplexer
The output 301 outputs the lower 4 bits of the 8-bit register 300 when the selection field sel of the multi-branch microinstruction is 0, and outputs the upper 4 bits of the 8-bit register when the selection signal sel is 1. 4-bit multiplexer
The 4-bit data corresponding to the output of 301 and the mask field "mask" of the multi-branch microinstruction are connected to 2-input AND gates 310 to 313, respectively, and the logical product is addressed to the address.
Supply the middle 4 bits of the register.

Next, the operation of this embodiment will be described using an example of the BCD encoding process. Now, by executing the transfer microinstruction,
It is assumed that 10111100b (BCh) is set in the 8-bit register 300. When the multi-branch microinstruction MJMP1 (proc-base, 1111b); is to be executed at the address 0100, the microorder LDMBR becomes active. At this time, each field of the multi-branch microinstruction is set as follows.

sel ... 1b base ... 001b mask ... 1111b Current value of address register 304 is 0000000000000000
0b, the upper 8 bits of the address register 304 are newly added.
The bits contain 00000001b and the next three bits contain the base value 001
In the next 4 bits, the output of the 2-input AND 310 to 313 is set in the next 4 bits. However, since the sel signal is 1, the upper 4-bit data 1011b of the 8-bit register 300 has the mask value 11
1011b, which is the logical product of 11b, is set. address·
The least significant bit of the register is always set to 0.

As a result of the above operation, the address register 304 stores 00000
00100110110b, that is, set to address 0136.

Similarly, the multi-branch microinstruction MJMP1 (proc-bas
e, 1111b); As a result, the address moves as follows.

These branch destination addresses have a proc-plus for processing a positive number and a proc-plus for processing a negative number as shown below.
minus, a branch microinstruction to proc-error for error processing JMP (proc-plus); JMP (proc-minus); and JMP (proc-error) are described, and after execution of the multi-branch microinstruction Control transitions to one of the procedures.

FIG. 9 shows the relationship between these procedures and the location of the multi-branch microinstruction.

In the above operation example, after control is transferred to address 0136, JMP (p
roc-minus); control is performed by execution of an instruction.
Move to the processing procedure for negative numbers described in.

Similarly, the upper 4 bits 1110b of the 8-bit register 300
Is set, proc- via address 013C
When the process proceeds to plus and the positive number process is set, and when 0010b is set, the process proceeds to proc-error via address 0124 to start a process procedure for the error.

Next, another operation in the conventional example will be described. In this operation example, as shown in FIG. 10, the value of an 8-bit status register (not shown) is stored in the 8-bit register 400.
It is assumed that it has been set by executing the transfer microinstruction. Each bit of the status register 400 is divided into three fields ST0 (3 bits), ST1 (2 bits) and ST2 (1 bit) as shown below. Bits 5-6
And bit 7. Bits 3 and 4 of status register 400 are undefined but undefined.

Use the following commands to check each field.

For example, when checking the ST1 field, if the content of ST1 is 00b, address 4; if 01b, address 8;
Address, if address 11, address 0E (each base address
control can be transferred to (adrs1).

In the embodiment of the present invention, the 8-bit parameter is divided into two, and 2, 4, 8, and 16 ways can be selected with a maximum of 16 ways.
By increasing the length of 200 and the length of the field sel for parameter selection of the multi-branch microinstruction, longer parameters are multiplexed and the multi-branch microinstruction with a shorter length provides more multi-branch microinstructions can do.

〔The invention's effect〕

As described above, by using the present invention, in a microprogram whose processing needs to be changed according to the content of a parameter, a short instruction word length that can perform a branch operation at high speed regardless of the length or value of the parameter is used. ,
Moreover, it is possible to provide micro-instructions with high versatility.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a general format of a conditional microinstruction, and FIG. 3 is an example of an information processing apparatus employing a conventional microprogram controller. FIG. 4, FIG. 4 is a diagram showing a general format of a packed BCD, FIG. 5 is a diagram showing a general format of a multi-branch microinstruction, and FIG. FIG. 7 is a drawing showing a specific embodiment of the present invention, FIG.
FIG. 9 is a diagram showing a specific format of a multi-branch microinstruction, FIG. 9 is a diagram showing a location relationship of procedures in BCD code processing, and FIG. 10 is a diagram showing a status register structure in another embodiment of the present invention. It is a drawing. 100: Address register, 101: Micro instruction memory, 102: Instruction latch, 103: Incrementer, 104
…… Instruction decoder, 105 …… Status generator, 106 ……
Data bus, 107 ... arithmetic logic unit, 108 ...
Branch signal generator, 109 ... Branch address generator, 110
... register file, 200 ... multiway branch register, 201 ... multiplexer, 202 ... multiway branch address generator, 203 ... address register, 204 ... instruction decoder, 300 ... 8 Bit latch, 301 ... 4-bit multiplexer, 302 ...
Multiway branch address generator, 303 ... 16
Bit address register, 310 to 313 ... 2-input AN
D, 400 ... 8-bit status register

Claims (1)

(57) [Claims] 1. A latch connected to a data bus and holding parameter information on the data bus by executing a transfer microinstruction, and extracting means for extracting predetermined predetermined bit string information from the parameter information held in the latch. And a means for selectively masking the data extracted by the extracting means with a branch microinstruction, wherein all or a part of the branch destination address is determined by directly using the masked data. Microprogram control device.