JPS641059A - Vector computing system - Google Patents

Vector computing system

Info

Publication number
JPS641059A
JPS641059A JP62165686A JP16568687A JPS641059A JP S641059 A JPS641059 A JP S641059A JP 62165686 A JP62165686 A JP 62165686A JP 16568687 A JP16568687 A JP 16568687A JP S641059 A JPS641059 A JP S641059A
Authority
JP
Japan
Prior art keywords
arithmetic operation
execution
arithmetic
completion
microinstruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62165686A
Other languages
Japanese (ja)
Other versions
JPH011059A (en
JPH0528870B2 (en
Inventor
Hideshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62165686A priority Critical patent/JPS641059A/en
Publication of JPH011059A publication Critical patent/JPH011059A/en
Publication of JPS641059A publication Critical patent/JPS641059A/en
Publication of JPH0528870B2 publication Critical patent/JPH0528870B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To immediately execute an arithmetic instruction, by instructing the start of the execution of an arithmetic operation for the next vector element replying to the completion of the execution of the arithmetic operation while a start instruction holding flag is set, and resetting the start instruction holding flag. CONSTITUTION:A microinstruction is read out from a control storage circuit 1, and is stored in a microinstruction register 3, and an arithmetic operation start bit S in the register 3 is supplied to an arithmetic control circuit 15. And while the arithmetic operation is executed, the signal S is set at a start instruction holding flag FF205 via a line 101 and an AND gate 212. The FF205, when the start instruction of the next arithmetic operation being issued by the microinstruction during the execution of the arithmetic operation, holds the instruction until the arithmetic operation under execution is completed. And the FF205 is reset corresponding to the completion of the execution of the arithmetic operation, and is set when the completion of the execution of the arithmetic operation and the start of the next execution are performed simultaneously.
JP62165686A 1986-07-16 1987-07-01 Vector computing system Granted JPS641059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165686A JPS641059A (en) 1986-07-16 1987-07-01 Vector computing system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP61-168626 1986-07-16
JP16862686 1986-07-16
JP62-41326 1987-02-26
JP62165686A JPS641059A (en) 1986-07-16 1987-07-01 Vector computing system

Publications (3)

Publication Number Publication Date
JPH011059A JPH011059A (en) 1989-01-05
JPS641059A true JPS641059A (en) 1989-01-05
JPH0528870B2 JPH0528870B2 (en) 1993-04-27

Family

ID=26490335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165686A Granted JPS641059A (en) 1986-07-16 1987-07-01 Vector computing system

Country Status (1)

Country Link
JP (1) JPS641059A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019526866A (en) * 2016-09-13 2019-09-19 エイアールエム リミテッド Vector multiply-add instruction

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134975A (en) * 1983-12-24 1985-07-18 Fujitsu Ltd Arithmetic circuit of sum of products

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134975A (en) * 1983-12-24 1985-07-18 Fujitsu Ltd Arithmetic circuit of sum of products

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019526866A (en) * 2016-09-13 2019-09-19 エイアールエム リミテッド Vector multiply-add instruction

Also Published As

Publication number Publication date
JPH0528870B2 (en) 1993-04-27

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