JPS55962A - Programmable sequence controller - Google Patents

Programmable sequence controller

Info

Publication number
JPS55962A
JPS55962A JP7451178A JP7451178A JPS55962A JP S55962 A JPS55962 A JP S55962A JP 7451178 A JP7451178 A JP 7451178A JP 7451178 A JP7451178 A JP 7451178A JP S55962 A JPS55962 A JP S55962A
Authority
JP
Japan
Prior art keywords
instruction
instructions
arithmetic
sequence
μpg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7451178A
Other languages
Japanese (ja)
Inventor
Katsuyuki Shimokawa
Kiyoshi Horiuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7451178A priority Critical patent/JPS55962A/en
Publication of JPS55962A publication Critical patent/JPS55962A/en
Pending legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE: To make it possible to constitute all sequence instruction including arithmetic instructions into one word by performing processes with microprogram μPG provided with instructions except mode instruction setting an arithmetic function, as to CPU on a μPG system.
CONSTITUTION: This controller consists of input-output point 13 meeting an external apparatus, memory unit 12 stored with data and sequence instructions, and μPG system CPU11 executing sequence arithmetic, and each sequence instruction is composed of one word of instruction part 41 and operand part 42. Then, μPG is provided with mode instructions for setting arithmetic functions, operand setting instructions, operator setting instructions, and arithmetic-result storage instructions, and an object to be set by each instruction is the operand part. When the mode instruction is sent, operand part 42 is temproarily stored in CPU11 and the stored arithmetic function is executed on receiving the operator setting instruction. Consequently, various arithmetic operations become possible by one-ward constitution without increasing the number of bits of any one of sequence instruction parts.
COPYRIGHT: (C)1980,JPO&Japio
JP7451178A 1978-06-20 1978-06-20 Programmable sequence controller Pending JPS55962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7451178A JPS55962A (en) 1978-06-20 1978-06-20 Programmable sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7451178A JPS55962A (en) 1978-06-20 1978-06-20 Programmable sequence controller

Publications (1)

Publication Number Publication Date
JPS55962A true JPS55962A (en) 1980-01-07

Family

ID=13549416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7451178A Pending JPS55962A (en) 1978-06-20 1978-06-20 Programmable sequence controller

Country Status (1)

Country Link
JP (1) JPS55962A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63183565U (en) * 1987-05-19 1988-11-25

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63183565U (en) * 1987-05-19 1988-11-25
JPH058527Y2 (en) * 1987-05-19 1993-03-03

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