JPS54107234A - Information processing unit - Google Patents

Information processing unit

Info

Publication number
JPS54107234A
JPS54107234A JP1424478A JP1424478A JPS54107234A JP S54107234 A JPS54107234 A JP S54107234A JP 1424478 A JP1424478 A JP 1424478A JP 1424478 A JP1424478 A JP 1424478A JP S54107234 A JPS54107234 A JP S54107234A
Authority
JP
Japan
Prior art keywords
privileged
flag
flop
information processing
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1424478A
Other languages
Japanese (ja)
Other versions
JPS6126091B2 (en
Inventor
Sada Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1424478A priority Critical patent/JPS54107234A/en
Publication of JPS54107234A publication Critical patent/JPS54107234A/en
Publication of JPS6126091B2 publication Critical patent/JPS6126091B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make the transfer from a slave mode to a privileged mode possible independently of calculation to shorten the processing time by controlling a privileged flag and a privileged control flag in the information processing unit.
CONSTITUTION: Instruction execution part 1 which stores the execution result of the instruction fetch instruction from a main memory is connected to AND circuits 2, 6 and 7, OR circuit 3 and privileged flag flip-flop 4 which indicates the operation mode of the unit through signal lines L1 to L5, and is connected to AND circuits 6, 7 and 2, inverter 5, privileged flag filp-flop 4, privileged control flag flip-flop 8 through signal lines L6 and L7.
COPYRIGHT: (C)1979,JPO&Japio
JP1424478A 1978-02-10 1978-02-10 Information processing unit Granted JPS54107234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1424478A JPS54107234A (en) 1978-02-10 1978-02-10 Information processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1424478A JPS54107234A (en) 1978-02-10 1978-02-10 Information processing unit

Publications (2)

Publication Number Publication Date
JPS54107234A true JPS54107234A (en) 1979-08-22
JPS6126091B2 JPS6126091B2 (en) 1986-06-19

Family

ID=11855669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1424478A Granted JPS54107234A (en) 1978-02-10 1978-02-10 Information processing unit

Country Status (1)

Country Link
JP (1) JPS54107234A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596376A (en) * 1982-06-30 1984-01-13 Anelva Corp Sputtering apparatus
JPS5963100A (en) * 1982-06-09 1984-04-10 エイ・ティ・アンド・ティ・コーポレーション Memory managing device for microprocessor

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0411996Y2 (en) * 1986-05-12 1992-03-24
JPH0411995Y2 (en) * 1986-05-19 1992-03-24
JPH0411994Y2 (en) * 1986-05-19 1992-03-24

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963100A (en) * 1982-06-09 1984-04-10 エイ・ティ・アンド・ティ・コーポレーション Memory managing device for microprocessor
JPS596376A (en) * 1982-06-30 1984-01-13 Anelva Corp Sputtering apparatus

Also Published As

Publication number Publication date
JPS6126091B2 (en) 1986-06-19

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