JPS569803A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS569803A
JPS569803A JP8396979A JP8396979A JPS569803A JP S569803 A JPS569803 A JP S569803A JP 8396979 A JP8396979 A JP 8396979A JP 8396979 A JP8396979 A JP 8396979A JP S569803 A JPS569803 A JP S569803A
Authority
JP
Japan
Prior art keywords
input
information
memory register
input memory
sequence controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8396979A
Other languages
Japanese (ja)
Inventor
Hiroshi Yaegashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8396979A priority Critical patent/JPS569803A/en
Publication of JPS569803A publication Critical patent/JPS569803A/en
Pending legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE: To increase an arithmetic processing speed by arranging an input memory register inside or near a main sequence controller body and by fetching information on the logical state of a desired input equipment from the input memory register.
CONSTITUTION: Parallel-input and series-output type shift register SR fetches information on the logical states of input equipments I0, I1, I2...In and it is stored in input memory register IMR being converted into series information. Then, this input memory register IMR is arranged inside or near main sequence control body CPU and in stationary operation, sequence controller body CPU receives the information on the logical state of a desired input equipment from input memory register IMR. Consequently, the propagation delay time of a signal accompanying the information input can be shortened and the arithmetic processing speed also increases.
COPYRIGHT: (C)1981,JPO&Japio
JP8396979A 1979-07-04 1979-07-04 Sequence controller Pending JPS569803A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8396979A JPS569803A (en) 1979-07-04 1979-07-04 Sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8396979A JPS569803A (en) 1979-07-04 1979-07-04 Sequence controller

Publications (1)

Publication Number Publication Date
JPS569803A true JPS569803A (en) 1981-01-31

Family

ID=13817361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8396979A Pending JPS569803A (en) 1979-07-04 1979-07-04 Sequence controller

Country Status (1)

Country Link
JP (1) JPS569803A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01106105A (en) * 1987-10-17 1989-04-24 Matsushita Electric Works Ltd Sequence controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01106105A (en) * 1987-10-17 1989-04-24 Matsushita Electric Works Ltd Sequence controller

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