JPS5729148A - Arithmetic control system - Google Patents

Arithmetic control system

Info

Publication number
JPS5729148A
JPS5729148A JP10413280A JP10413280A JPS5729148A JP S5729148 A JPS5729148 A JP S5729148A JP 10413280 A JP10413280 A JP 10413280A JP 10413280 A JP10413280 A JP 10413280A JP S5729148 A JPS5729148 A JP S5729148A
Authority
JP
Japan
Prior art keywords
shift control
signal
shift
processor
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10413280A
Other languages
Japanese (ja)
Inventor
Toshihiko Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10413280A priority Critical patent/JPS5729148A/en
Publication of JPS5729148A publication Critical patent/JPS5729148A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To increase an arithmetic processing speed by shortening a shift control time, by exercising shift cintrol by selecting a shift control pulse by a shift indication signal in a processor which performs arithmetic processing by clock pulses.
CONSTITUTION: When a shift control signal S supplied to a control terminal (a) is a 0, an AND circuit 3 is opened and a pulse signal A is supplied as an output signal C from an output terminal (b) to the shifting circuit of a processor. When the shift control signal S is a 1, namely, during shift control, an AND circuit 4 is opened, and a pulse signal B is sent out as the output signal C. Therefore, when the shift control is required, clock pulses differing in period are supplied to the processor only by sending an instruction whose prescribed bit has been changed.
COPYRIGHT: (C)1982,JPO&Japio
JP10413280A 1980-07-29 1980-07-29 Arithmetic control system Pending JPS5729148A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10413280A JPS5729148A (en) 1980-07-29 1980-07-29 Arithmetic control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10413280A JPS5729148A (en) 1980-07-29 1980-07-29 Arithmetic control system

Publications (1)

Publication Number Publication Date
JPS5729148A true JPS5729148A (en) 1982-02-17

Family

ID=14372576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10413280A Pending JPS5729148A (en) 1980-07-29 1980-07-29 Arithmetic control system

Country Status (1)

Country Link
JP (1) JPS5729148A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63298521A (en) * 1987-05-29 1988-12-06 Nec Corp Bit scan circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63298521A (en) * 1987-05-29 1988-12-06 Nec Corp Bit scan circuit

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