JPS5560332A - Automatic setting delay circuit - Google Patents

Automatic setting delay circuit

Info

Publication number
JPS5560332A
JPS5560332A JP13342978A JP13342978A JPS5560332A JP S5560332 A JPS5560332 A JP S5560332A JP 13342978 A JP13342978 A JP 13342978A JP 13342978 A JP13342978 A JP 13342978A JP S5560332 A JPS5560332 A JP S5560332A
Authority
JP
Japan
Prior art keywords
signal
delay time
terminal
counter
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13342978A
Other languages
Japanese (ja)
Inventor
Yoshinori Chiwaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13342978A priority Critical patent/JPS5560332A/en
Publication of JPS5560332A publication Critical patent/JPS5560332A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE: To make it possible to set automatically adequate delay time by an automatic setting delay circuit for a data processor, by generating several output pulse signals, differing in delay time, on receiving one input pulse signal.
CONSTITUTION: One input pulse from input terminal 2 is supplied to delay circuit 11, which sends out eight kinds of signals differing in delay time to selector circuit 12, and one kind of signal indicated by a selective input (contents of counter 35) is transmitted to output terminal 7. A phase dofference between the rise of a reference signal from reference signal terminal 4 and the fall of a signal from output terminal 7 is detected by JKFFs 14, 21, 22, and 23 and gates 15, 16 and 25, and minimized under the control of counter 18, register 27, comparator circuit 28, counter 35, and JKFF44 and after selective setting ends, a signal from terminal 8 and that of delay time selected from output terminal 7 are sent out.
COPYRIGHT: (C)1980,JPO&Japio
JP13342978A 1978-10-30 1978-10-30 Automatic setting delay circuit Pending JPS5560332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13342978A JPS5560332A (en) 1978-10-30 1978-10-30 Automatic setting delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13342978A JPS5560332A (en) 1978-10-30 1978-10-30 Automatic setting delay circuit

Publications (1)

Publication Number Publication Date
JPS5560332A true JPS5560332A (en) 1980-05-07

Family

ID=15104558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13342978A Pending JPS5560332A (en) 1978-10-30 1978-10-30 Automatic setting delay circuit

Country Status (1)

Country Link
JP (1) JPS5560332A (en)

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