JPS54123977A - Logic circuit apparatus - Google Patents

Abstract

PURPOSE: To enable the margin for delay time of the logic circuit of only the apparatus under measurement by providing a pulse generating means which generates clock signals of a fixed and a period clock delaying means which delays the clock signals set-time-variably.

CONSTITUTION: The clock signals from a pulse generator 25 which generates the clock signals of a fixed period are supplied to registers 22, 23 by a first clock distributing system 26 and are delayed at an arbitrary time by a delay time control circuit 27 and are supplied from a second clock distributing system 28 to the register 22. The logic circuit 24 forms the input signals to the registers 22 and 23 based on the logic signals given from input terminal 21 from the outside and the register 22. The outputs of the logic circuit 24 are stored in the register 23, are compared with a malfunction detecting means and when the malufunction is detected, the delay time having been set in the delay time control circuit 27 becomes the maximum time of delay margin.

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