JPS54123977A - Logic circuit apparatus - Google Patents

Logic circuit apparatus

Info

Publication number
JPS54123977A
JPS54123977A JP3134278A JP3134278A JPS54123977A JP S54123977 A JPS54123977 A JP S54123977A JP 3134278 A JP3134278 A JP 3134278A JP 3134278 A JP3134278 A JP 3134278A JP S54123977 A JPS54123977 A JP S54123977A
Authority
JP
Japan
Prior art keywords
clock
logic circuit
delay time
register
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3134278A
Other languages
Japanese (ja)
Other versions
JPH0334258B2 (en
Inventor
Masaaki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3134278A priority Critical patent/JPS54123977A/en
Publication of JPS54123977A publication Critical patent/JPS54123977A/en
Publication of JPH0334258B2 publication Critical patent/JPH0334258B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE: To enable the margin for delay time of the logic circuit of only the apparatus under measurement by providing a pulse generating means which generates clock signals of a fixed and a period clock delaying means which delays the clock signals set-time-variably.
CONSTITUTION: The clock signals from a pulse generator 25 which generates the clock signals of a fixed period are supplied to registers 22, 23 by a first clock distributing system 26 and are delayed at an arbitrary time by a delay time control circuit 27 and are supplied from a second clock distributing system 28 to the register 22. The logic circuit 24 forms the input signals to the registers 22 and 23 based on the logic signals given from input terminal 21 from the outside and the register 22. The outputs of the logic circuit 24 are stored in the register 23, are compared with a malfunction detecting means and when the malufunction is detected, the delay time having been set in the delay time control circuit 27 becomes the maximum time of delay margin.
COPYRIGHT: (C)1979,JPO&Japio
JP3134278A 1978-03-17 1978-03-17 Logic circuit apparatus Granted JPS54123977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3134278A JPS54123977A (en) 1978-03-17 1978-03-17 Logic circuit apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3134278A JPS54123977A (en) 1978-03-17 1978-03-17 Logic circuit apparatus

Publications (2)

Publication Number Publication Date
JPS54123977A true JPS54123977A (en) 1979-09-26
JPH0334258B2 JPH0334258B2 (en) 1991-05-22

Family

ID=12328550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3134278A Granted JPS54123977A (en) 1978-03-17 1978-03-17 Logic circuit apparatus

Country Status (1)

Country Link
JP (1) JPS54123977A (en)

Also Published As

Publication number Publication date
JPH0334258B2 (en) 1991-05-22

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