JPS5538604A - Memory device - Google Patents

Abstract

PURPOSE:To simplify timing needed to operate a memory device by operating each holding circuit at common holding timing and also by generating a fixed write control signal on the basis of this timing. CONSTITUTION:Data input 5 and address input 6 are held at a rise point of clock signal 20 and the held data are inputted as input signals 31 and 32 to memory integrated circuit 1. Those inputs and write signal 21 inputted in parallel are held in a rise of signal 20 to obtain write indication signal holding output 34, which is inputted to AND circuit 25. The other input to circuit 25, rising on the basis of the rise of signal 20 lagging by the delay time of delay circuit 23, is applied through write pulse generating circuit 24. The output of circuit 25 is applied as control signal 11 to circuit 1. At this time, the delay time of circuit 23 and the pulse width of circuit 24 are set greater than that required in terms of characteristics of circuit 1 and a signal before and after the clock signal is also set greater than the sum of the above-mentioned delay time and pulse width, an holding time needed for circuit 1.