JPS5798174A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPS5798174A JPS5798174A JP55173676A JP17367680A JPS5798174A JP S5798174 A JPS5798174 A JP S5798174A JP 55173676 A JP55173676 A JP 55173676A JP 17367680 A JP17367680 A JP 17367680A JP S5798174 A JPS5798174 A JP S5798174A
- Authority
- JP
- Japan
- Prior art keywords
- state
- semiconductor storage
- address information
- storage device
- selecting signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To obtain a storage device which is capable of inputting an address information asynchronously, and has decreased danger of a malfunction in case of non-selection, by inputting the address information through a through-latching circuit controlled by a block selecting signal. CONSTITUTION:One semiconductor storage cell designated by an address information applied by address signals A0-A9 is selected from a semiconductor storage cell group 25 in a block selected by a block selecting signal BS. Such a semiconductor storage device is provided with a through-latching circuit 23 by which an output state is varied following an input state while the block selecting signal BS is in a selecting state, and after the time when the block selecting signal BS has been transferred to a nonselecting state from the selecting state, the output is held at a state of its transition time. In this way, the address information is inputted through this through-latching circuit 23.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55173676A JPS5798174A (en) | 1980-12-09 | 1980-12-09 | Semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55173676A JPS5798174A (en) | 1980-12-09 | 1980-12-09 | Semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5798174A true JPS5798174A (en) | 1982-06-18 |
Family
ID=15965026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55173676A Pending JPS5798174A (en) | 1980-12-09 | 1980-12-09 | Semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5798174A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4750839A (en) * | 1985-08-07 | 1988-06-14 | Texas Instruments Incorporated | Semiconductor memory with static column decode and page mode addressing capability |
-
1980
- 1980-12-09 JP JP55173676A patent/JPS5798174A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4750839A (en) * | 1985-08-07 | 1988-06-14 | Texas Instruments Incorporated | Semiconductor memory with static column decode and page mode addressing capability |
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