JPS5729146A - Logical circuit including memory array - Google Patents

Logical circuit including memory array

Info

Publication number
JPS5729146A
JPS5729146A JP10307380A JP10307380A JPS5729146A JP S5729146 A JPS5729146 A JP S5729146A JP 10307380 A JP10307380 A JP 10307380A JP 10307380 A JP10307380 A JP 10307380A JP S5729146 A JPS5729146 A JP S5729146A
Authority
JP
Japan
Prior art keywords
memory array
logical circuit
circuit
input signal
signal group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10307380A
Other languages
Japanese (ja)
Inventor
Masanobu Takahashi
Shigehiro Funatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10307380A priority Critical patent/JPS5729146A/en
Publication of JPS5729146A publication Critical patent/JPS5729146A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To test a logical circuit part except a memory array by providing a compressing circuit and a selector circuit, by permitting the data input signal of the memory array to by-pass the memory array as well as an address input signal. CONSTITUTION:When a logical circuit including a memory array 1 is to be tested, an output signal group 23 from a compressing circuit 21 propagates to the output signal group 8 of a selector circuit 3 once the control signal 11 of the selector circuit 3 is driven with logic 1 in order to test a logical circuit part except the memory array 1. Consequently, the memory array 1 is by-passed completely and the entire logical circuit part including a part where a data input signal group 4 and an address input signal group 5 to the memory array 1 are suppplied is tested easily.
JP10307380A 1980-07-29 1980-07-29 Logical circuit including memory array Pending JPS5729146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10307380A JPS5729146A (en) 1980-07-29 1980-07-29 Logical circuit including memory array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10307380A JPS5729146A (en) 1980-07-29 1980-07-29 Logical circuit including memory array

Publications (1)

Publication Number Publication Date
JPS5729146A true JPS5729146A (en) 1982-02-17

Family

ID=14344467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10307380A Pending JPS5729146A (en) 1980-07-29 1980-07-29 Logical circuit including memory array

Country Status (1)

Country Link
JP (1) JPS5729146A (en)

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