JPS5736331A - Bus line device - Google Patents

Bus line device

Info

Publication number
JPS5736331A
JPS5736331A JP11207280A JP11207280A JPS5736331A JP S5736331 A JPS5736331 A JP S5736331A JP 11207280 A JP11207280 A JP 11207280A JP 11207280 A JP11207280 A JP 11207280A JP S5736331 A JPS5736331 A JP S5736331A
Authority
JP
Japan
Prior art keywords
bus
data
address signal
circuit
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11207280A
Other languages
Japanese (ja)
Other versions
JPS614122B2 (en
Inventor
Kazuo Yamaguchi
Kiyoharu Oikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11207280A priority Critical patent/JPS5736331A/en
Publication of JPS5736331A publication Critical patent/JPS5736331A/en
Publication of JPS614122B2 publication Critical patent/JPS614122B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To shorten the access time of high speed data extremely speedily by arranging a bus connected to a high speed circuit 13 such as storage circuit group more close to an output terminal or data register than the bus connected to a low speed circuit such as an output port group. CONSTITUTION:When a port address signal is ''1'' and a memory address signal is ''0'', data from an output port group 11 are transmitted to a data register 16 through a bus 12, a select circuit 15 and a bus 14. Data from a storage circuit group 13 are transmitted to the register 16 through the bus 14 when the memory address signal is ''1''. Even if the port address signal is ''1'', the memory address signal is inversed by an inversion circuit 17 and a select signal with level ''0'' is inputted to the select circuit 15. Thus, the bus 12 is separated from the bus 14 and the data from the port group 11 are not transmitted to the output terminal or register 16 through the bus 14.
JP11207280A 1980-08-14 1980-08-14 Bus line device Granted JPS5736331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11207280A JPS5736331A (en) 1980-08-14 1980-08-14 Bus line device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11207280A JPS5736331A (en) 1980-08-14 1980-08-14 Bus line device

Publications (2)

Publication Number Publication Date
JPS5736331A true JPS5736331A (en) 1982-02-27
JPS614122B2 JPS614122B2 (en) 1986-02-07

Family

ID=14577361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11207280A Granted JPS5736331A (en) 1980-08-14 1980-08-14 Bus line device

Country Status (1)

Country Link
JP (1) JPS5736331A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144857A (en) * 1984-01-06 1985-07-31 Nec Corp Cpu peripheral circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144857A (en) * 1984-01-06 1985-07-31 Nec Corp Cpu peripheral circuit

Also Published As

Publication number Publication date
JPS614122B2 (en) 1986-02-07

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