JPS5736489A - Decoding circuit - Google Patents

Decoding circuit

Info

Publication number
JPS5736489A
JPS5736489A JP11195080A JP11195080A JPS5736489A JP S5736489 A JPS5736489 A JP S5736489A JP 11195080 A JP11195080 A JP 11195080A JP 11195080 A JP11195080 A JP 11195080A JP S5736489 A JPS5736489 A JP S5736489A
Authority
JP
Japan
Prior art keywords
output
decoding circuit
fets
turned
output lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11195080A
Other languages
Japanese (ja)
Inventor
Koichi Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11195080A priority Critical patent/JPS5736489A/en
Publication of JPS5736489A publication Critical patent/JPS5736489A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/10Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To simplify the circuit and to decrease a chip size, by making unnecessary an inverting input signal in a decoding circuit using a field effect transistor. CONSTITUTION:An output of all output lines 17-20 is made to ''0'' by making a clear signal to ''1'' after input signals I1, I2 are determined and then the clear signal CL is returned to ''0''. In this case, for example, the input signals I1, I2 are both at ''0'', ''1'' is outputted to the output line 17 since FETs 9, 10 are turned off. ''0'' output is given to the output lines 18, 19, 20 since FETs 26, 27 and 28, 29 are turned off. That is, the output line 17 is selected. One of the output lines 18, 19, 20 can be selected similarly, when the input signal is in other state than stated above.
JP11195080A 1980-08-11 1980-08-11 Decoding circuit Pending JPS5736489A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11195080A JPS5736489A (en) 1980-08-11 1980-08-11 Decoding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11195080A JPS5736489A (en) 1980-08-11 1980-08-11 Decoding circuit

Publications (1)

Publication Number Publication Date
JPS5736489A true JPS5736489A (en) 1982-02-27

Family

ID=14574207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11195080A Pending JPS5736489A (en) 1980-08-11 1980-08-11 Decoding circuit

Country Status (1)

Country Link
JP (1) JPS5736489A (en)

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