JPS56106451A - Multiplication/isolation circuit - Google Patents

Multiplication/isolation circuit

Info

Publication number
JPS56106451A
JPS56106451A JP914380A JP914380A JPS56106451A JP S56106451 A JPS56106451 A JP S56106451A JP 914380 A JP914380 A JP 914380A JP 914380 A JP914380 A JP 914380A JP S56106451 A JPS56106451 A JP S56106451A
Authority
JP
Japan
Prior art keywords
multiplication
output data
isolation
circuit
register sfr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP914380A
Other languages
Japanese (ja)
Inventor
Kenichi Hashimoto
Makoto Sudo
Ryoichi Shinoda
Hiroyuki Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP914380A priority Critical patent/JPS56106451A/en
Publication of JPS56106451A publication Critical patent/JPS56106451A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To reduce the scale of circuit, by using a circuit in common for both multiplication and its isolation. CONSTITUTION:The shift register SFR has a shift with the fall of the clock CLK2 and when the mode control signal MC is at a low level. The parallel output data Poutn-Pout 1 are delivered from the output terminals Q1-Qn of the shift register SFR. In other words, the serial input data Sin is converted into the parallel output data to carry out the isolation of multiplication. In this instant, the parallel input data Pij is set to the register SFR to deliver the serial output data Sout. That is, a multiplication is carried out.
JP914380A 1980-01-29 1980-01-29 Multiplication/isolation circuit Pending JPS56106451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP914380A JPS56106451A (en) 1980-01-29 1980-01-29 Multiplication/isolation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP914380A JPS56106451A (en) 1980-01-29 1980-01-29 Multiplication/isolation circuit

Publications (1)

Publication Number Publication Date
JPS56106451A true JPS56106451A (en) 1981-08-24

Family

ID=11712392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP914380A Pending JPS56106451A (en) 1980-01-29 1980-01-29 Multiplication/isolation circuit

Country Status (1)

Country Link
JP (1) JPS56106451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330098A (en) * 1986-07-24 1988-02-08 Nippon Telegr & Teleph Corp <Ntt> Shift register type time switch and network constituted by same switch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330098A (en) * 1986-07-24 1988-02-08 Nippon Telegr & Teleph Corp <Ntt> Shift register type time switch and network constituted by same switch

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