JPS5539920A - Pipeline multiplication system - Google Patents

Pipeline multiplication system

Info

Publication number
JPS5539920A
JPS5539920A JP11152178A JP11152178A JPS5539920A JP S5539920 A JPS5539920 A JP S5539920A JP 11152178 A JP11152178 A JP 11152178A JP 11152178 A JP11152178 A JP 11152178A JP S5539920 A JPS5539920 A JP S5539920A
Authority
JP
Japan
Prior art keywords
outputs
module
sel
input terminal
adders
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11152178A
Other languages
Japanese (ja)
Other versions
JPS5629306B2 (en
Inventor
Kensaku Fujii
Masaharu Terauchi
Shiro Kikuchi
Hitoshi Imagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP11152178A priority Critical patent/JPS5539920A/en
Publication of JPS5539920A publication Critical patent/JPS5539920A/en
Publication of JPS5629306B2 publication Critical patent/JPS5629306B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To provide a pipeline multiplication system by which the correct results can be obtained in any case.
CONSTITUTION: A primary level module Mi, an intermediate module Mm determined by the level number of the multiplier factor and the multiplicand and the terminal module Mt are longitudinally connected. In the respective module, there are provided the selection circuits Sel1, Seln, Selt. When the inputs are not generated in the respective timing signal input ends T1, Tn, Tt, the outputs b0, bn, bt of the AND circuits Po, Pn, Pt are transmitted through the delay element D to input terminal of all the adders FA1, FAn, FAt as outputs D0, Dn-1, Dt-1. When the input is generated in the timing signal input terminal T1, Tn, Tt, the outputs of AND gate A1, An, At, the switching is carried out so as to transmit the outputs of AND gates A1, An, At to the input terminal b of all the adders FA1, FAn, FAt through the delay element D in the same manner as the above.
COPYRIGHT: (C)1980,JPO&Japio
JP11152178A 1978-09-11 1978-09-11 Pipeline multiplication system Granted JPS5539920A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11152178A JPS5539920A (en) 1978-09-11 1978-09-11 Pipeline multiplication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11152178A JPS5539920A (en) 1978-09-11 1978-09-11 Pipeline multiplication system

Publications (2)

Publication Number Publication Date
JPS5539920A true JPS5539920A (en) 1980-03-21
JPS5629306B2 JPS5629306B2 (en) 1981-07-07

Family

ID=14563426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11152178A Granted JPS5539920A (en) 1978-09-11 1978-09-11 Pipeline multiplication system

Country Status (1)

Country Link
JP (1) JPS5539920A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63227208A (en) * 1987-03-17 1988-09-21 Matsushita Electric Ind Co Ltd Digital signal processing circuit
JPH04123727U (en) * 1991-04-19 1992-11-10 細川 誠二 Dump truck with chute

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63227208A (en) * 1987-03-17 1988-09-21 Matsushita Electric Ind Co Ltd Digital signal processing circuit
JPH04123727U (en) * 1991-04-19 1992-11-10 細川 誠二 Dump truck with chute

Also Published As

Publication number Publication date
JPS5629306B2 (en) 1981-07-07

Similar Documents

Publication Publication Date Title
JPS5776634A (en) Digital signal processor
JPS5650439A (en) Binary multiplier cell circuit
JPS5539920A (en) Pipeline multiplication system
JPS5694435A (en) Multiplying circuit
JPS5663649A (en) Parallel multiplication apparatus
JPS5748141A (en) Address conversion system
JPS539450A (en) Primary digital overall areas passing circuit
JPS5386539A (en) Arithmetic unit
JPS553066A (en) Composite multiplier
JPS56106451A (en) Multiplication/isolation circuit
JPS55138141A (en) Printer share mechanism
JPS54104216A (en) Receiver for digital multi-frequency signal
JPS5685127A (en) Digital signal processor
JPS54101238A (en) Parity circuit
JPS55108051A (en) Buffer system for data in multiplier
JPS643734A (en) Multiplication circuit
JPS5494856A (en) Non-circulation type filter
JPS5378743A (en) Multiplier
JPS6433672A (en) Cumulative multiplier
JPS55102921A (en) Signal processor
JPS55104126A (en) Phase comparison circuit
JPS54132144A (en) Multiple process system
JPS5498544A (en) Multiplier for complex number
JPS5592017A (en) Digital filter
JPS55119741A (en) Operation circuit