JPS55108051A - Buffer system for data in multiplier - Google Patents

Buffer system for data in multiplier

Info

Publication number
JPS55108051A
JPS55108051A JP1384579A JP1384579A JPS55108051A JP S55108051 A JPS55108051 A JP S55108051A JP 1384579 A JP1384579 A JP 1384579A JP 1384579 A JP1384579 A JP 1384579A JP S55108051 A JPS55108051 A JP S55108051A
Authority
JP
Japan
Prior art keywords
multiplier
data
register
buffer
next stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1384579A
Other languages
Japanese (ja)
Other versions
JPS5729739B2 (en
Inventor
Fumio Amano
Kazuo Murano
Shigeyuki Umigami
Yasukazu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1384579A priority Critical patent/JPS55108051A/en
Publication of JPS55108051A publication Critical patent/JPS55108051A/en
Publication of JPS5729739B2 publication Critical patent/JPS5729739B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To enable to reduce the scale of hardware, by using the space caused with the shift addition to inhibit the input to the multiplier of the data for next stage operation as the buffer.
CONSTITUTION: The multiplicand in the multiplier and multiplicand register 6 in the multiplier register 3 is multiplied with the shift addition, and the next stage operation data is directly via the input terminals 1 and 4 or from the buffer register 5' to the space in the register caused in each clock. Further, in case of execution of multiplication, the input of the next stage operation data to the multiplier 7 is inhibited with the inhibit control lines 9 and 10 so that the data for next stage operation can not be affected to the operation at the present stage. In this case, by using the space caused with the shift addition as the buffer, the buffer register is made small in size or made unnecessary to reduce the scale of the hardware.
COPYRIGHT: (C)1980,JPO&Japio
JP1384579A 1979-02-10 1979-02-10 Buffer system for data in multiplier Granted JPS55108051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1384579A JPS55108051A (en) 1979-02-10 1979-02-10 Buffer system for data in multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1384579A JPS55108051A (en) 1979-02-10 1979-02-10 Buffer system for data in multiplier

Publications (2)

Publication Number Publication Date
JPS55108051A true JPS55108051A (en) 1980-08-19
JPS5729739B2 JPS5729739B2 (en) 1982-06-24

Family

ID=11844603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1384579A Granted JPS55108051A (en) 1979-02-10 1979-02-10 Buffer system for data in multiplier

Country Status (1)

Country Link
JP (1) JPS55108051A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7278251B2 (en) 2020-12-02 2023-05-19 プライムプラネットエナジー＆ソリューションズ株式会社 Laser processing equipment

Also Published As

Publication number Publication date
JPS5729739B2 (en) 1982-06-24

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