JPS5654562A - Competing circuit - Google Patents

Competing circuit

Info

Publication number
JPS5654562A
JPS5654562A JP13018779A JP13018779A JPS5654562A JP S5654562 A JPS5654562 A JP S5654562A JP 13018779 A JP13018779 A JP 13018779A JP 13018779 A JP13018779 A JP 13018779A JP S5654562 A JPS5654562 A JP S5654562A
Authority
JP
Japan
Prior art keywords
circuit
request
signal
output
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13018779A
Other languages
Japanese (ja)
Inventor
Jiyouji Satou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13018779A priority Critical patent/JPS5654562A/en
Publication of JPS5654562A publication Critical patent/JPS5654562A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To select a request signal effectively by selecting one signal while holding the others in a queue when signal processors request to use a shared source, such as a shared data file, simultaneously.
CONSTITUTION: For example, request input signals r1 and r2 of request signal input lines 1 and 2 are held at level "1" in the same sampling period. Counters 21 and 22 receives clock signals to hold output lines at "1" and further holds AND circuits 24 and 25, and 27 and 28 at "1". Their outputs are inputted to NOR circuit 34, which generates an output of "0" to close AND circuit 45, so that the output of clock circuit 46 will be stopped. On the other hand, outputs of NAND circuits 30 and 31 show "0" and use request signal "1" is outputted from NAND circuit 33. Consequently, when use request signals are generated at a time, one of them is selected and the others are held in a queue. Consequently effective signal selection can be carried out.
COPYRIGHT: (C)1981,JPO&Japio
JP13018779A 1979-10-09 1979-10-09 Competing circuit Pending JPS5654562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13018779A JPS5654562A (en) 1979-10-09 1979-10-09 Competing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13018779A JPS5654562A (en) 1979-10-09 1979-10-09 Competing circuit

Publications (1)

Publication Number Publication Date
JPS5654562A true JPS5654562A (en) 1981-05-14

Family

ID=15028149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13018779A Pending JPS5654562A (en) 1979-10-09 1979-10-09 Competing circuit

Country Status (1)

Country Link
JP (1) JPS5654562A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129567A (en) * 1982-01-27 1983-08-02 Nec Corp Multi-system control device
JPS58129565A (en) * 1982-01-27 1983-08-02 Nec Corp Multi-system control device
JPH06161952A (en) * 1990-07-03 1994-06-10 Internatl Business Mach Corp <Ibm> Arbitration device of access request

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129567A (en) * 1982-01-27 1983-08-02 Nec Corp Multi-system control device
JPS58129565A (en) * 1982-01-27 1983-08-02 Nec Corp Multi-system control device
JPS6334499B2 (en) * 1982-01-27 1988-07-11 Nippon Electric Co
JPH06161952A (en) * 1990-07-03 1994-06-10 Internatl Business Mach Corp <Ibm> Arbitration device of access request

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