JPS6421656A - Read/write system for data - Google Patents

Read/write system for data

Info

Publication number
JPS6421656A
JPS6421656A JP17953787A JP17953787A JPS6421656A JP S6421656 A JPS6421656 A JP S6421656A JP 17953787 A JP17953787 A JP 17953787A JP 17953787 A JP17953787 A JP 17953787A JP S6421656 A JPS6421656 A JP S6421656A
Authority
JP
Japan
Prior art keywords
data
circle
read
processor
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17953787A
Other languages
Japanese (ja)
Inventor
Hisayoshi Hayasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17953787A priority Critical patent/JPS6421656A/en
Publication of JPS6421656A publication Critical patent/JPS6421656A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To easily realize a large scale integrated circuit by obtaining a common input output terminal and reduced a constituting element per register. CONSTITUTION:One instruction is issued from a processor 10 and by utilizing a time until the next instruction is issued, the shift processing of plural registers 1(1)-1(4), read data and write data are selected according to a read/write instruction 3 (in circle) from the processor 10. In the same way, even for data to be loaded on a data bus (a), which data of read data 1' (in circle) or write data 1 is selected is determined by controlling a state buffer 4 according to the read/write instruction 3 from the processor 10. Further, for a shift clock 4 (in circle) an address 2 (in circle) transmitted from the processor 10 through an address a' is converted in a decoder circuit 5 according to the output of the shift clock 4 (in circle). Thus, a common input output line is obtained between an address and data and the number of the input output terminals is cut down.
JP17953787A 1987-07-17 1987-07-17 Read/write system for data Pending JPS6421656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17953787A JPS6421656A (en) 1987-07-17 1987-07-17 Read/write system for data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17953787A JPS6421656A (en) 1987-07-17 1987-07-17 Read/write system for data

Publications (1)

Publication Number Publication Date
JPS6421656A true JPS6421656A (en) 1989-01-25

Family

ID=16067488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17953787A Pending JPS6421656A (en) 1987-07-17 1987-07-17 Read/write system for data

Country Status (1)

Country Link
JP (1) JPS6421656A (en)

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