JPS5647979A - Decoding system - Google Patents

Decoding system

Info

Publication number
JPS5647979A
JPS5647979A JP12186479A JP12186479A JPS5647979A JP S5647979 A JPS5647979 A JP S5647979A JP 12186479 A JP12186479 A JP 12186479A JP 12186479 A JP12186479 A JP 12186479A JP S5647979 A JPS5647979 A JP S5647979A
Authority
JP
Japan
Prior art keywords
data
terminals
supplied
bit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12186479A
Other languages
Japanese (ja)
Inventor
Koichi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12186479A priority Critical patent/JPS5647979A/en
Publication of JPS5647979A publication Critical patent/JPS5647979A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To reduce various logic circuits by providing a semiconductor memory with a decoding function and combinational circuit function by reading combinational logic data by supplying normal input data and various condition signals to the address input of the semiconductor memory. CONSTITUTION:ROM21 is equipped with terminals A0-A9 to which 10-bit address data are inputted and 4-bit data output terminals D0-D3; and data DATA to be decoded are supplied from the central processor to terminals A2-A9, and condition signals, e.g. selective timing signals SELA and SELB, are supplied to terminals A0 and A1. In respective addresses of ROM21, on the other hand, 4-bit combinational logic data D0-D3 are fixedly stored corresponding to respective inputs. Then, when each input is supplied at fixed timing, data D0-D3 are outputted.
JP12186479A 1979-09-21 1979-09-21 Decoding system Pending JPS5647979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12186479A JPS5647979A (en) 1979-09-21 1979-09-21 Decoding system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12186479A JPS5647979A (en) 1979-09-21 1979-09-21 Decoding system

Publications (1)

Publication Number Publication Date
JPS5647979A true JPS5647979A (en) 1981-04-30

Family

ID=14821811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12186479A Pending JPS5647979A (en) 1979-09-21 1979-09-21 Decoding system

Country Status (1)

Country Link
JP (1) JPS5647979A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60233751A (en) * 1984-05-04 1985-11-20 Omron Tateisi Electronics Co Address decoding circuit
JPS63214995A (en) * 1987-03-04 1988-09-07 Ando Electric Co Ltd Memory selecting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60233751A (en) * 1984-05-04 1985-11-20 Omron Tateisi Electronics Co Address decoding circuit
JPS63214995A (en) * 1987-03-04 1988-09-07 Ando Electric Co Ltd Memory selecting circuit

Similar Documents

Publication Publication Date Title
JPS55128641A (en) Controlling system for vehicle
JPS5647979A (en) Decoding system
JPS5338373A (en) Ic for watch
JPS55110324A (en) Unit control circuit
JPS641050A (en) Computer system provided with byte order conversion mechanism
JPS57113169A (en) Microcomputer
JPS57111669A (en) Output system for conjugation form of word
JPS57117056A (en) Microcomputer device
JPS6476486A (en) Memory ic
JPS6464073A (en) Image memory
JPS6419580A (en) Dual port memory circuit
JPS5745657A (en) Storage device
JPS5556262A (en) Operation hysteresis retention system
JPS5597077A (en) Memory circuit
JPS5690692A (en) Signal processing system of electronic switch board
JPS54142018A (en) Memory control system
JPS6435639A (en) Rom/ram memory access switching circuit
JPS6459547A (en) Microcomputer
JPS5494839A (en) Memory unit
JPS56101247A (en) Audio output device
JPS6421656A (en) Read/write system for data
JPS55124871A (en) Graph processor
JPS5547547A (en) Control device
JPH01201890A (en) Read only memory control circuit
JPS6470993A (en) Dual port ram