JPS6476486A - Memory ic - Google Patents

Memory ic

Info

Publication number
JPS6476486A
JPS6476486A JP62235322A JP23532287A JPS6476486A JP S6476486 A JPS6476486 A JP S6476486A JP 62235322 A JP62235322 A JP 62235322A JP 23532287 A JP23532287 A JP 23532287A JP S6476486 A JPS6476486 A JP S6476486A
Authority
JP
Japan
Prior art keywords
address
signal
inverse
memory
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62235322A
Other languages
Japanese (ja)
Other versions
JP2974071B2 (en
Inventor
Kikuo Muramatsu
Osamu Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62235322A priority Critical patent/JP2974071B2/en
Priority to DE19883831530 priority patent/DE3831530A1/en
Publication of JPS6476486A publication Critical patent/JPS6476486A/en
Priority to US07/579,230 priority patent/US5243701A/en
Application granted granted Critical
Publication of JP2974071B2 publication Critical patent/JP2974071B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To realize the system of high performance by connecting a memory IC by selectively using only a low-order 2<n>-bit data bus while responding to a high-order address activating signal and a bus selecting signal when an access is executed at every unit of 2<n> bits. CONSTITUTION:When a CPU not shown in a figure, is made access to an EPROM, namely, a memory IC 100 at every unit of 16 bits, address signals Ao-A14, which appear on an address bus 4, are the address signals of an even number and the least significant address signal A0 goes to an L level. The address signals A1-A14 of 14 bits are respectively impressed to address input terminals 61 and 71 of respective EPROMs 9 and 10. When an address on the address bus 4 is decided, a bite-high-enable signal, the inverse of BHE and a chip enable signal, the inverse of CE from the CPU go to be the L of an activating condition. With responding to the L of these signals, the inverse of BHE and the inverse of CE, the address signal on the address data bus 4 is fetched into the EPROMs 9 and 10 of the memory IC 100.
JP62235322A 1987-09-17 1987-09-17 Memory IC Expired - Fee Related JP2974071B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62235322A JP2974071B2 (en) 1987-09-17 1987-09-17 Memory IC
DE19883831530 DE3831530A1 (en) 1987-09-17 1988-09-16 Data processing circuit to process data with different bit lengths
US07/579,230 US5243701A (en) 1987-09-17 1990-09-06 Method of and system for processing data having bit length variable with modes of operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235322A JP2974071B2 (en) 1987-09-17 1987-09-17 Memory IC

Publications (2)

Publication Number Publication Date
JPS6476486A true JPS6476486A (en) 1989-03-22
JP2974071B2 JP2974071B2 (en) 1999-11-08

Family

ID=16984390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235322A Expired - Fee Related JP2974071B2 (en) 1987-09-17 1987-09-17 Memory IC

Country Status (2)

Country Link
JP (1) JP2974071B2 (en)
DE (1) DE3831530A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410144A (en) * 1990-04-27 1992-01-14 Matsushita Electric Ind Co Ltd Data transfer circuit
US7561475B2 (en) 2006-01-04 2009-07-14 Samsung Electronics Co., Ltd. Flash memory controller
JP2010027202A (en) * 2009-10-30 2010-02-04 Renesas Technology Corp Magnetic storage device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08212132A (en) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp Storage device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850693A (en) * 1981-09-18 1983-03-25 Omron Tateisi Electronics Co Memory access method for memory system
JPS6257043A (en) * 1985-09-06 1987-03-12 Nec Corp Memory circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850693A (en) * 1981-09-18 1983-03-25 Omron Tateisi Electronics Co Memory access method for memory system
JPS6257043A (en) * 1985-09-06 1987-03-12 Nec Corp Memory circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410144A (en) * 1990-04-27 1992-01-14 Matsushita Electric Ind Co Ltd Data transfer circuit
US7561475B2 (en) 2006-01-04 2009-07-14 Samsung Electronics Co., Ltd. Flash memory controller
JP2010027202A (en) * 2009-10-30 2010-02-04 Renesas Technology Corp Magnetic storage device

Also Published As

Publication number Publication date
DE3831530A1 (en) 1989-03-30
JP2974071B2 (en) 1999-11-08

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Legal Events

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