JPS54129944A - Arithmetic controller - Google Patents

Arithmetic controller

Info

Publication number
JPS54129944A
JPS54129944A JP3762378A JP3762378A JPS54129944A JP S54129944 A JPS54129944 A JP S54129944A JP 3762378 A JP3762378 A JP 3762378A JP 3762378 A JP3762378 A JP 3762378A JP S54129944 A JPS54129944 A JP S54129944A
Authority
JP
Japan
Prior art keywords
imd
bus
field
bits
bit position
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3762378A
Other languages
Japanese (ja)
Inventor
Yutaka Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3762378A priority Critical patent/JPS54129944A/en
Publication of JPS54129944A publication Critical patent/JPS54129944A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce steps in number with the bit length of an IMD made variable by equipping a CPU on a microprogram-stored control system with a bus through which immediate data IMD is transmitted to a desirable bit position.
CONSTITUTION: The CPU is provided with micro-data register MRDR registering microprogram μPG; some of the contents of it is for a control field, and the other is sent out to A-BUS as IMD. Bits 19 to 21 of MRDR are used for the assignment of the bit position of A-BUS for a number sisplayed in the DATA field of the FI field. For example, when bits 19 to 21 of the FI field are supposed to be "001", gate G2 is opened by a timing signal and the number of the DATA field is transmitted to bits 14 to 23 of A-BUS. Therefore, since the transmission bit position of IMD becomes variable, flexibility is given to the control, the bit length of IMD can be elongated, and steps of μPG can also be reduced in number, so that the arithmetic speed will become high.
COPYRIGHT: (C)1979,JPO&Japio
JP3762378A 1978-03-31 1978-03-31 Arithmetic controller Pending JPS54129944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3762378A JPS54129944A (en) 1978-03-31 1978-03-31 Arithmetic controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3762378A JPS54129944A (en) 1978-03-31 1978-03-31 Arithmetic controller

Publications (1)

Publication Number Publication Date
JPS54129944A true JPS54129944A (en) 1979-10-08

Family

ID=12502752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3762378A Pending JPS54129944A (en) 1978-03-31 1978-03-31 Arithmetic controller

Country Status (1)

Country Link
JP (1) JPS54129944A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57199041A (en) * 1981-06-03 1982-12-06 Fuji Xerox Co Ltd Bit data processing device
JPS59133647A (en) * 1982-11-26 1984-08-01 インモス，リミテツド Computer and operation of computer equipment
JPS6488838A (en) * 1987-09-30 1989-04-03 Takeshi Sakamura Data processor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57199041A (en) * 1981-06-03 1982-12-06 Fuji Xerox Co Ltd Bit data processing device
JPH0215086B2 (en) * 1981-06-03 1990-04-11 Fuji Xerox Co Ltd
JPS59133647A (en) * 1982-11-26 1984-08-01 インモス，リミテツド Computer and operation of computer equipment
US4724517A (en) * 1982-11-26 1988-02-09 Inmos Limited Microcomputer with prefixing functions
JPH0470652B2 (en) * 1982-11-26 1992-11-11 Inmos Ltd
JPS6488838A (en) * 1987-09-30 1989-04-03 Takeshi Sakamura Data processor

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