JPS5498149A - Microprocessor - Google Patents

Microprocessor

Info

Publication number
JPS5498149A
JPS5498149A JP503278A JP503278A JPS5498149A JP S5498149 A JPS5498149 A JP S5498149A JP 503278 A JP503278 A JP 503278A JP 503278 A JP503278 A JP 503278A JP S5498149 A JPS5498149 A JP S5498149A
Authority
JP
Japan
Prior art keywords
cpu
registers
ports
microprocessor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP503278A
Other languages
Japanese (ja)
Inventor
Kensaku Wada
Koichi Fujita
Masaharu Kimura
Masashi Kominai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP503278A priority Critical patent/JPS5498149A/en
Publication of JPS5498149A publication Critical patent/JPS5498149A/en
Pending legal-status Critical Current

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  • Microcomputers (AREA)

Abstract

PURPOSE: To reduce the number of registers without degrading CPU functions in a microprocessor.
CONSTITUTION: The I/O shared port for CPU transfers information supplied to port part 3 to the data bus 4 direction through input circuit 1 by an INPUT instruction, and latch-holds information sent from CPU through data bus 4 in output circuit 2 consisting of registers by an OUTPUT instruction, and then transfers it to the terminal equipment direction from read port part 3 by the next OUTPUT instruction. The microprocessor has m-bit I/O ports P1 to Pn consisting of m-number I/O shared ports like this. Unused ports are not connected to the external, and can hold temporarily contents of CPU in input circuit 2 by OUTPUT and INPUT instructions, so that it is possible to share the register of input circuit 2 with registers of CPU.
COPYRIGHT: (C)1979,JPO&Japio
JP503278A 1978-01-19 1978-01-19 Microprocessor Pending JPS5498149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP503278A JPS5498149A (en) 1978-01-19 1978-01-19 Microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP503278A JPS5498149A (en) 1978-01-19 1978-01-19 Microprocessor

Publications (1)

Publication Number Publication Date
JPS5498149A true JPS5498149A (en) 1979-08-02

Family

ID=11600123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP503278A Pending JPS5498149A (en) 1978-01-19 1978-01-19 Microprocessor

Country Status (1)

Country Link
JP (1) JPS5498149A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59206969A (en) * 1983-05-11 1984-11-22 Hitachi Ltd Microprocessor
JPS62145454A (en) * 1985-12-20 1987-06-29 Nec Corp Input and output port control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59206969A (en) * 1983-05-11 1984-11-22 Hitachi Ltd Microprocessor
JPS62145454A (en) * 1985-12-20 1987-06-29 Nec Corp Input and output port control circuit
JPH0556549B2 (en) * 1985-12-20 1993-08-19 Nippon Electric Co

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