JPS54148445A - Data transfer control unit - Google Patents

Data transfer control unit

Info

Publication number
JPS54148445A
JPS54148445A JP5652878A JP5652878A JPS54148445A JP S54148445 A JPS54148445 A JP S54148445A JP 5652878 A JP5652878 A JP 5652878A JP 5652878 A JP5652878 A JP 5652878A JP S54148445 A JPS54148445 A JP S54148445A
Authority
JP
Japan
Prior art keywords
control unit
data transfer
register
sets
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5652878A
Other languages
Japanese (ja)
Inventor
Akira Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5652878A priority Critical patent/JPS54148445A/en
Publication of JPS54148445A publication Critical patent/JPS54148445A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the unnecessary data transfer and thus to enhance the data transfer efficiency by altering through the input/output control unit both the data transfer start address indicated by the input/output command word and the count number by the indication given from the peripheral control unit.
CONSTITUTION: Primary part 10 of the input/output control unit draws out the input command word via bus 11 and then sets it to registers 12W15, and then sends the command and the flag only to primary part 10' of the peripheral control unit. Part 10' sets them to registers 12' and 13' and then supplies to decoder 115 to send the count alteration information to part 10 via control circuit 116. Part 10 sets the information to register 16, calculates the contents of control circuit 19 at arithmetic circuit 18 based on the state of register 16 as well as the contents of register 12 and 13 respectively, and then sets reach calculation result to register 14 and 15 via bus 111. In this way, both the data transfer start address and the data transfer count number can be altered based on the direction given from the peripheral control unit.
COPYRIGHT: (C)1979,JPO&Japio
JP5652878A 1978-05-15 1978-05-15 Data transfer control unit Pending JPS54148445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5652878A JPS54148445A (en) 1978-05-15 1978-05-15 Data transfer control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5652878A JPS54148445A (en) 1978-05-15 1978-05-15 Data transfer control unit

Publications (1)

Publication Number Publication Date
JPS54148445A true JPS54148445A (en) 1979-11-20

Family

ID=13029595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5652878A Pending JPS54148445A (en) 1978-05-15 1978-05-15 Data transfer control unit

Country Status (1)

Country Link
JP (1) JPS54148445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63109560A (en) * 1986-10-28 1988-05-14 Fujitsu Ltd Command control system in file controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63109560A (en) * 1986-10-28 1988-05-14 Fujitsu Ltd Command control system in file controller
JPH0524541B2 (en) * 1986-10-28 1993-04-08 Fujitsu Ltd

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