JPS5532155A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5532155A
JPS5532155A JP10524678A JP10524678A JPS5532155A JP S5532155 A JPS5532155 A JP S5532155A JP 10524678 A JP10524678 A JP 10524678A JP 10524678 A JP10524678 A JP 10524678A JP S5532155 A JPS5532155 A JP S5532155A
Authority
JP
Japan
Prior art keywords
instruction
circuit
modified bit
operand
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10524678A
Other languages
Japanese (ja)
Inventor
Susumu Sawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10524678A priority Critical patent/JPS5532155A/en
Publication of JPS5532155A publication Critical patent/JPS5532155A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To enable to execute the processing corresponding to natural languages easily, by modifying the processing modes given with the operation code with the number of operands and the length of instruction.
CONSTITUTION: The instruction read out from the main memory unit 1 is set to the register 4 via the registers 2 and 3, and the format of instruction is classified via the comparison circuits 7-0 and 7-1. That is, when the AND circuit 14 is ON, "100" is set to the modified bit M1 in the control memory address register 9, and when the AND circuit 16 is ON, "010" is set to the modified bit M1 with the constant length operand instruction, and when the AND circuit 15 or 17 is ON, "001" is set to the modified bit M1 with the undefined length operand instruction. Thus, the processing corresponding to natural language can easily be executed by checking the operand number information and/or instruction information and by determining the processing mode by the instruction words.
COPYRIGHT: (C)1980,JPO&Japio
JP10524678A 1978-08-29 1978-08-29 Data processor Pending JPS5532155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10524678A JPS5532155A (en) 1978-08-29 1978-08-29 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10524678A JPS5532155A (en) 1978-08-29 1978-08-29 Data processor

Publications (1)

Publication Number Publication Date
JPS5532155A true JPS5532155A (en) 1980-03-06

Family

ID=14402281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10524678A Pending JPS5532155A (en) 1978-08-29 1978-08-29 Data processor

Country Status (1)

Country Link
JP (1) JPS5532155A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155457A (en) * 1982-03-10 1983-09-16 Nec Corp Information processing device
JPH08263284A (en) * 1981-05-22 1996-10-11 Data General Corp Digital computer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08263284A (en) * 1981-05-22 1996-10-11 Data General Corp Digital computer system
JPS58155457A (en) * 1982-03-10 1983-09-16 Nec Corp Information processing device
JPH0128416B2 (en) * 1982-03-10 1989-06-02 Nippon Denki Kk

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