JPS5696336A - Processing system for multilayer level microprogram - Google Patents

Processing system for multilayer level microprogram

Info

Publication number
JPS5696336A
JPS5696336A JP17319379A JP17319379A JPS5696336A JP S5696336 A JPS5696336 A JP S5696336A JP 17319379 A JP17319379 A JP 17319379A JP 17319379 A JP17319379 A JP 17319379A JP S5696336 A JPS5696336 A JP S5696336A
Authority
JP
Japan
Prior art keywords
instruction
register
processing system
load instruction
microprogram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17319379A
Other languages
Japanese (ja)
Other versions
JPS6218933B2 (en
Inventor
Masahiro Kawakatsu
Eizo Fujisaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17319379A priority Critical patent/JPS6218933B2/ja
Publication of JPS5696336A publication Critical patent/JPS5696336A/en
Publication of JPS6218933B2 publication Critical patent/JPS6218933B2/ja
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To improve the data processing capability, by accessing the first and the second control storages simultaneously in the system where control storages are accessed on a basis of instructions.
CONSTITUTION: When the machine language instruction fetched from the memory is transferred and the Load instruction is entered in instruction register 2, the Load instruction is set to machine operation register MOPR3 by the one-fetch micro instruction, and simultaneously, the picoprogram accessed by the micro operation code is set to picostorage PS data register 12. The OP code of the Load instruction set to MOPR3 is set to PS address register 10 also, and PS 9 is read simultaneously with reading of ROM4. At this time, a part of the output of ROM4 is set to CS address register 5, and CS 6 is read, and the microprogram of CS 6 is executed.
COPYRIGHT: (C)1981,JPO&Japio
JP17319379A 1979-12-28 1979-12-28 Expired JPS6218933B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17319379A JPS6218933B2 (en) 1979-12-28 1979-12-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17319379A JPS6218933B2 (en) 1979-12-28 1979-12-28

Publications (2)

Publication Number Publication Date
JPS5696336A true JPS5696336A (en) 1981-08-04
JPS6218933B2 JPS6218933B2 (en) 1987-04-25

Family

ID=15955811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17319379A Expired JPS6218933B2 (en) 1979-12-28 1979-12-28

Country Status (1)

Country Link
JP (1) JPS6218933B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831451A (en) * 1981-08-18 1983-02-24 Nec Corp Controlling device for microprogram
JPS62102333A (en) * 1985-10-29 1987-05-12 Fujitsu Ltd Microprogram control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831451A (en) * 1981-08-18 1983-02-24 Nec Corp Controlling device for microprogram
JPS6226725B2 (en) * 1981-08-18 1987-06-10 Nippon Electric Co
JPS62102333A (en) * 1985-10-29 1987-05-12 Fujitsu Ltd Microprogram control system

Also Published As

Publication number Publication date
JPS6218933B2 (en) 1987-04-25

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