JPS55153053A - Information processor - Google Patents

Information processor

Info

Publication number
JPS55153053A
JPS55153053A JP6072179A JP6072179A JPS55153053A JP S55153053 A JPS55153053 A JP S55153053A JP 6072179 A JP6072179 A JP 6072179A JP 6072179 A JP6072179 A JP 6072179A JP S55153053 A JPS55153053 A JP S55153053A
Authority
JP
Japan
Prior art keywords
arithmetic
read
length
control
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6072179A
Other languages
Japanese (ja)
Other versions
JPS5756746B2 (en
Inventor
Kenichi Wada
Masahiro Hashimoto
Chikahiko Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6072179A priority Critical patent/JPS55153053A/en
Publication of JPS55153053A publication Critical patent/JPS55153053A/en
Publication of JPS5756746B2 publication Critical patent/JPS5756746B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To perform high-speed read/write processing without increasing test conditions by separately controlling the read length and write length of an operand by the advanced control unit and arithmetic unit of a pipeline control computer.
CONSTITUTION: Instructions are read from main memory 6 to advanced control unit(ADVC)1 via data line 100 and decoded there for the processing of address calculation. Then, ADVC1 sends the initial micro instruction address of an instruction to control memory 5 via address line 107 and also sends read length and write length to arithmetic status circuit 2 via data lines 105 and 104 to actuate an arithmetic unit. At an arithmetic stage, arithmetic status circuit 2, operator 4 and ADVC1 are brought under control according to microinstructions stored in control memory 5. Control memory 5 normally reads two micro instructions and test circuit 3 selects either of them.
COPYRIGHT: (C)1980,JPO&Japio
JP6072179A 1979-05-17 1979-05-17 Information processor Granted JPS55153053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6072179A JPS55153053A (en) 1979-05-17 1979-05-17 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6072179A JPS55153053A (en) 1979-05-17 1979-05-17 Information processor

Publications (2)

Publication Number Publication Date
JPS55153053A true JPS55153053A (en) 1980-11-28
JPS5756746B2 JPS5756746B2 (en) 1982-12-01

Family

ID=13150417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6072179A Granted JPS55153053A (en) 1979-05-17 1979-05-17 Information processor

Country Status (1)

Country Link
JP (1) JPS55153053A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60238937A (en) * 1984-05-11 1985-11-27 Nec Corp Precedence controlling device
JPS60238935A (en) * 1984-05-11 1985-11-27 Nec Corp Precedence controlling device
JPS60238934A (en) * 1984-05-11 1985-11-27 Nec Corp Precedence controlling device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60238937A (en) * 1984-05-11 1985-11-27 Nec Corp Precedence controlling device
JPS60238935A (en) * 1984-05-11 1985-11-27 Nec Corp Precedence controlling device
JPS60238934A (en) * 1984-05-11 1985-11-27 Nec Corp Precedence controlling device

Also Published As

Publication number Publication date
JPS5756746B2 (en) 1982-12-01

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