JPS57103530A - Channel controlling system - Google Patents

Channel controlling system

Info

Publication number
JPS57103530A
JPS57103530A JP17983080A JP17983080A JPS57103530A JP S57103530 A JPS57103530 A JP S57103530A JP 17983080 A JP17983080 A JP 17983080A JP 17983080 A JP17983080 A JP 17983080A JP S57103530 A JPS57103530 A JP S57103530A
Authority
JP
Japan
Prior art keywords
stored
register
command
storage
storage area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17983080A
Other languages
Japanese (ja)
Inventor
Noboru Yamamoto
Toshiaki Ihi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17983080A priority Critical patent/JPS57103530A/en
Publication of JPS57103530A publication Critical patent/JPS57103530A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To store various types of statuses and commands without increasing the capacity of an interface register, by setting only the head address where the instruction and the status of a main storage are stored onto the interface register. CONSTITUTION:A subprocessor 13 actuates a DMA controlling circuit 6 and reads the command at the head of a command address 16 of a main storage 2 which is stored in a command register 7 of an interface register 8. The transmission data is read from a storage area 18 when necessary and fetched to the device 13 and a substorate 15 to carry out a process according to the instruction. If the status information to be informed to a process result main processor 1 exists, the status information is stored in the same way in a status storage area 17 at and after the head address of the storage 2 indicated to the register 8. Furthermore, the data if any to be sent to the processor 1 is stored in a storage area 19.
JP17983080A 1980-12-19 1980-12-19 Channel controlling system Pending JPS57103530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17983080A JPS57103530A (en) 1980-12-19 1980-12-19 Channel controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17983080A JPS57103530A (en) 1980-12-19 1980-12-19 Channel controlling system

Publications (1)

Publication Number Publication Date
JPS57103530A true JPS57103530A (en) 1982-06-28

Family

ID=16072631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17983080A Pending JPS57103530A (en) 1980-12-19 1980-12-19 Channel controlling system

Country Status (1)

Country Link
JP (1) JPS57103530A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61202256A (en) * 1985-03-05 1986-09-08 Fujitsu Ltd Channel trouble processing system
US7257662B2 (en) 2003-07-02 2007-08-14 Fujitsu Limited Status reporting apparatus and status reporting method
US7757016B2 (en) 2007-02-01 2010-07-13 Fujitsu Limited Data transfer device, semiconductor integrated circuit, and processing status notification method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61202256A (en) * 1985-03-05 1986-09-08 Fujitsu Ltd Channel trouble processing system
US7257662B2 (en) 2003-07-02 2007-08-14 Fujitsu Limited Status reporting apparatus and status reporting method
US7757016B2 (en) 2007-02-01 2010-07-13 Fujitsu Limited Data transfer device, semiconductor integrated circuit, and processing status notification method

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