JPS5599633A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS5599633A
JPS5599633A JP694879A JP694879A JPS5599633A JP S5599633 A JPS5599633 A JP S5599633A JP 694879 A JP694879 A JP 694879A JP 694879 A JP694879 A JP 694879A JP S5599633 A JPS5599633 A JP S5599633A
Authority
JP
Japan
Prior art keywords
memory
data
data transfer
cpu
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP694879A
Other languages
Japanese (ja)
Inventor
Tsuneo Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP694879A priority Critical patent/JPS5599633A/en
Publication of JPS5599633A publication Critical patent/JPS5599633A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To realize the data transfer with a high efficiency between the data processors by providing at least more than one unit of the information transfer memory to each data terminal unit and thus securing the direct control for the memory at the data transfer time.
CONSTITUTION: For the data transfer between the processors, at least more than one unit of information transfer memory DTM is provided with every data terminal unit and within the memory which is capable of the direct reading and writing to microprocessor μ-CPU. Thus the memory function is secured through the μ-CPU. At the data transmission time, memory DTM is cut off completely and temporarily from the program of the μ-CPU. And thus the data transfer is carried out directly between memory DTM and the data terminal unit. The interruption function also completes simultaneously with end of the data transfer.
COPYRIGHT: (C)1980,JPO&Japio
JP694879A 1979-01-23 1979-01-23 Data transfer control system Pending JPS5599633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP694879A JPS5599633A (en) 1979-01-23 1979-01-23 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP694879A JPS5599633A (en) 1979-01-23 1979-01-23 Data transfer control system

Publications (1)

Publication Number Publication Date
JPS5599633A true JPS5599633A (en) 1980-07-29

Family

ID=11652448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP694879A Pending JPS5599633A (en) 1979-01-23 1979-01-23 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS5599633A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61290561A (en) * 1985-06-19 1986-12-20 Mitsubishi Electric Corp Interface controller circuit
JPS63311466A (en) * 1987-06-13 1988-12-20 Fujitsu Ten Ltd Write or read system
US5170469A (en) * 1987-05-06 1992-12-08 Fujitsu Ten Limited Data transfer apparatus and data transfer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61290561A (en) * 1985-06-19 1986-12-20 Mitsubishi Electric Corp Interface controller circuit
US5170469A (en) * 1987-05-06 1992-12-08 Fujitsu Ten Limited Data transfer apparatus and data transfer system
JPS63311466A (en) * 1987-06-13 1988-12-20 Fujitsu Ten Ltd Write or read system

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