JPS5534336A - Buffer memory control method - Google Patents

Buffer memory control method

Info

Publication number
JPS5534336A
JPS5534336A JP10650178A JP10650178A JPS5534336A JP S5534336 A JPS5534336 A JP S5534336A JP 10650178 A JP10650178 A JP 10650178A JP 10650178 A JP10650178 A JP 10650178A JP S5534336 A JPS5534336 A JP S5534336A
Authority
JP
Japan
Prior art keywords
buffer memory
data
circuit
command
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10650178A
Other languages
Japanese (ja)
Inventor
Nobuyuki Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10650178A priority Critical patent/JPS5534336A/en
Publication of JPS5534336A publication Critical patent/JPS5534336A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To enhance the hit efficiency of the buffer memory by determining the order of priority by taking into consideration the quality of the data in the buffer memory which retains the copy of the main memory.
CONSTITUTION: The information processing device comprises the buffer memory 7 retaining the copy of the main memory, the priority order determining circuit 11 for determining the priority order in the block, the command control circuit 3 for carrying out decording the command code and the control of the command performance. At this time, when the data which will not be used in future, for example, the data designated by the second operand portion of the editing command is made access, it is informed to the circuit 11 from the control circuit 3. The circuit 11 gives it the lowest priority order. In this manner, taking into consideration the quality of the data, the algorithm of the determination of order is changed, so that the data which will not be used is retained in the buffer memory, so that the hit efficiency can be enhanced.
COPYRIGHT: (C)1980,JPO&Japio
JP10650178A 1978-08-31 1978-08-31 Buffer memory control method Pending JPS5534336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10650178A JPS5534336A (en) 1978-08-31 1978-08-31 Buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10650178A JPS5534336A (en) 1978-08-31 1978-08-31 Buffer memory control method

Publications (1)

Publication Number Publication Date
JPS5534336A true JPS5534336A (en) 1980-03-10

Family

ID=14435175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10650178A Pending JPS5534336A (en) 1978-08-31 1978-08-31 Buffer memory control method

Country Status (1)

Country Link
JP (1) JPS5534336A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002510085A (en) * 1998-03-31 2002-04-02 インテル・コーポレーション Shared cache structure for temporary and non-temporary instructions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002510085A (en) * 1998-03-31 2002-04-02 インテル・コーポレーション Shared cache structure for temporary and non-temporary instructions

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