JPS563485A - Buffer memory device - Google Patents

Buffer memory device

Info

Publication number
JPS563485A
JPS563485A JP7781979A JP7781979A JPS563485A JP S563485 A JPS563485 A JP S563485A JP 7781979 A JP7781979 A JP 7781979A JP 7781979 A JP7781979 A JP 7781979A JP S563485 A JPS563485 A JP S563485A
Authority
JP
Japan
Prior art keywords
memory
storage
control circuit
access control
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7781979A
Other languages
Japanese (ja)
Inventor
Akihiko Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7781979A priority Critical patent/JPS563485A/en
Publication of JPS563485A publication Critical patent/JPS563485A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To hold the contents of the present buffer memory and then increase the process efficiency, by inhibiting the storage of the information via the storage inhibition signal to the buffer memory.
CONSTITUTION: Buffer memory 20 stores part of the data of main memory 30 as the copy. And the address memory part, the address coincidence detecting circuit, the access control circuit to memory 30 and the writing circuit each of memory 20 are included in memory control circuit 21. Memory access control circuit 22 produces the storage inhibition signal to memory 20 in addition to the normal memory access control signal such as the memory access, the memory command. With generation of this storage inhibition signal, the storage of the information into memory 20 is inhibited in case the data or the program which will rarely be used again is read out of memory 30. Thus the unnecessary replacement is avoided for the effective information in memory 20.
COPYRIGHT: (C)1981,JPO&Japio
JP7781979A 1979-06-20 1979-06-20 Buffer memory device Pending JPS563485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7781979A JPS563485A (en) 1979-06-20 1979-06-20 Buffer memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7781979A JPS563485A (en) 1979-06-20 1979-06-20 Buffer memory device

Publications (1)

Publication Number Publication Date
JPS563485A true JPS563485A (en) 1981-01-14

Family

ID=13644633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7781979A Pending JPS563485A (en) 1979-06-20 1979-06-20 Buffer memory device

Country Status (1)

Country Link
JP (1) JPS563485A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60153554A (en) * 1984-01-23 1985-08-13 Hitachi Ltd Input/output control circuit
JPS60246457A (en) * 1984-05-21 1985-12-06 Fujitsu Ltd Memory access controlling circuit
JPS6159554A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Cache memory control circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60153554A (en) * 1984-01-23 1985-08-13 Hitachi Ltd Input/output control circuit
JPS60246457A (en) * 1984-05-21 1985-12-06 Fujitsu Ltd Memory access controlling circuit
JPH0347542B2 (en) * 1984-05-21 1991-07-19 Fujitsu Ltd
JPS6159554A (en) * 1984-08-31 1986-03-27 Hitachi Ltd Cache memory control circuit

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