JPH0347542B2 - - Google Patents

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a data processing device having a channel buffer (CHB) between a main storage unit (MUS) and a channel processing unit (CHP). The present invention relates to a memory access control circuit that accesses a main storage unit (MSU) without referring to the main storage unit (MSU).

(b) Technical Background Generally, in a data processing device that has a channel buffer (hereinafter referred to as CHB) between a main storage unit (hereinafter referred to as MSU) and a channel processing unit (hereinafter referred to as CHP), the CHB is Considering that MSU access is performed in channel (CH) units and the access addresses are consecutive on the MSU address, it is divided into channel (CH) units and placed in the memory control unit (MCU). .

And each channel (CH) has 2
Block CHB is allocated, and the size of one block is 64 bytes.

Figure 1 shows the above continuous data transfer.
The operation at CHB is schematically shown. In this diagram,
D0 to D15 indicate byte numbers of continuous data. First, in the case of fetching data, when fetching from a channel (CH), refer to CHB, and if the desired data does not exist, load 64 bytes of data from MSU to CHB, and at the same time 8 bytes
Transfer directly to CHP. Thereafter, it operates to fetch continuous data in units of 8 bytes from CHB.

When reading the following 8 bytes of data within the above 64 bytes from the CHB (for example, block 0) and sending it to the CHP, a specific 8 bytes within the 64 bytes (D6 or D7 in the figure) is fetched. Then, the prefetch control circuit is activated and controlled to load the next 64 consecutive bytes on the address into the other block (for example, block 1).

"For data storage" In case of store access from channel (CH), refer to CHB, select any block (for example, block 0) according to the inside of its tag part, and access the store data. byte mark (8 bytes indicating which 8-byte area is stored)
bit data).

If a subsequent store access requires a different block, the other block (e.g.
The block 1) is controlled to write store data.

At this time (for example, when storing to D8), register the address of the block written in the previous store access (i.e., block 0) in the moveout queue (MO QUEUE), and then use the moveout queue (MO QUEUE). QUEUE),
The block is controlled to be moved out to the MSU.

"For fetches other than data [Channel Adrus language (CAW), channel command word (CCW)]" There is data at the address registered in the above data fetch operation by referring to the CHB (recognized by the CHB TAG part's variance). If this is possible, there will be unnecessary data, so after invalidating that data, access the MSU and read the information (CAW,
CCW) directly to the CHP. In this case, the information, i.e. CAW, CCW
is not continuous data, so it is controlled not to be loaded to CHB. This operation guarantees the order of the CAW and CCW accesses with respect to data transfer.

Furthermore, if the result of referencing the CHB matches the address registered in the store operation, the block is moved out to the MSU and then the MSU is fetched.

"When storing something other than data [channel status word (CSW)]" If the CHB is referenced and there is a block in which the above data is stored (recognized by the CHB TAG part's valid value), data is still being transferred. , and all of them (up to 2
block) moves out to the MSU, and after the move-out operation is completed, the CSW store access is controlled to be executed to the MSU.
Also in this case, the channel status word (CSW) is not written to the CHB. This operation guarantees the order of the CSW store access and data transfer.

In view of the fact that treating accesses other than the data listed above in the same manner as general data will cause problems in efficient use of channel and channel OVER-RUN countermeasures, the present invention was filed. Person is Japanese Patent Publication No. 57-205885
In the publication ``Channel Buffer Control System'', detailed operations and effects for accessing data other than these are disclosed in the ``Claims'' column and the ``Detailed Description of the Invention'' column.

Access to data other than data by CHP requires fetches such as the channel address word (CAW), channel command word (CCW), input/output status word (UCW), channel status word (CSW), input/output status word (UCW), etc. ) and other stores.

The present invention relates to a method for effectively performing non-data access, particularly access to input/output status words (UCW) without the need to maintain order with data transfer.

(c) Prior art and problems In a data processing device having a CHB between the MUS and CHP, subchannel information, dynamic address translation (DAT) table information, etc. are stored in a fixed area of the MSU and are In the conventional system, access to the input/output status word (hereinafter referred to as UCW), which does not need to maintain order with data transfer, is also controlled as described above. Therefore, (1) UCW access is delayed depending on the state of the CHB, resulting in a longer "busy" period of the CHP port, which has a negative effect on the throughput of data access in the CHP.

(2) Generally, UCW access is performed in parallel with data transfer, so CHB is referenced each time,
When data that is being transferred is invalidated or moved out, the number of times blocks are loaded and moved out increases, causing a problem that reduces data access throughput in CHP.

(d) Purpose of the invention In view of the above-mentioned conventional drawbacks, the present invention provides an MSU and
In a data processing device that has a CHB between it and the CHP, even if there is no CHB, an address exception event occurs when the MSU is accessed from the CHP (for example, an access when the UCW area is accessed during normal data access) When the CHP accesses the above UCW area of the MSU, the flag signal “CHP UCW” is sent as a means of detecting exceptions, etc.
When the CHP accesses the UCW area using the flag signal,
The purpose is to provide an access method suitable for the characteristics of the UCW.

(e) Structure of the Invention According to the present invention, a central processing unit (CPU), a channel processing unit (CHP) that controls a plurality of channels (CH), a main storage unit (MSU), A memory control unit (MCU) that performs access control to the main storage unit (MSU) and interface control between the central processing unit (CPU) and the channel processing unit (CHP), and a memory control unit (MCU) that controls access to the main storage unit (MSU) and the channel processing unit. In a data processing device that has a channel buffer (CHB) between the device (CHP) and a channel buffer (CHB), general data from the channel (CH) that needs to maintain the order of data transfer, and some control information (CAW ,CCW,
CSW), access to the general data is via the channel buffer (CHB),
Access to some of the above control information is performed by referring to the channel buffer (CHB), but access to control information (UCW) that does not need to maintain order with the data transfer is performed by referring to the channel buffer (CHB). This is achieved by providing a method with the ability to directly access the main storage unit (MSU) without having to perform input/output status area (UCW) accesses from the channel processing unit (CHP). However, the contents of the channel buffer (CHB) remain unchanged, which has the advantage of preventing a decrease in throughput in the channel processing unit (CHP).

(f) Examples of the invention First, to summarize the gist of the present invention, the present invention includes the following:
Focusing on the fact that when a memory access from CHP is executed to UCW, the flub "CHP UCW" indicating UCW access is sent from CHP, and using this flub signal, without referring to CHB (i.e.,
) and access the MSU directly.

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 2 is a block diagram showing an embodiment of the present invention, in which 1 and 2 are CHP address registers (CHPAR), 11 and 21 are channel (CH) identification registers, and 12 and 22 are CHP number divisions. , 13
is the UCW flub necessary to carry out the present invention, 3
0 and 31 are CHB tag sections (CHB TAG), which correspond to blocks 0 and 1, respectively. 40,41
is a comparison circuit (C) provided for each block, and CHP address register (CHPAR) 1
Contents and CHB tag section (CHB TAG) 31, 31
The address part (ADDR) of the tag part is compared bit by bit, and if they match, a match signal is output and tag part match registers 60 and 61 are set. 8 is a UCW access flag, which is set on by the output signal of the UCM flag 13 only when the CHP accesses the UCW on the MSU. 9 is a converter (DEC) that decodes the contents of tag part match registers 60, 61 and valid hit flags 70, 71 (described later), and converts the data part (CHB
DATA) Generate part of 32 Adrus. 1
01, 102, 103 are CHB data part (CHB
DATA) Address register for 32, 1
For 01 and 102, the outputs of the channel (CH) identification register 21 and CHP number identification section 22 are set, and for 103, the output of the converter (DEC) 9 is set.

33 is CHB data register (CHPDR), 34
is the CHP store data register (CHPSTDR), 3
5 is a CHP fetch data register (CHPFCHDR), 50 and 51 are AND circuits with inhibit inputs, and 70 and 71 are valid bit flags, which correspond to blocks 0 and 1, respectively.

Now, when memory access is performed from CHP to MSU, CHP address register (CHPAR)
The memory address is set to 1, the channel number for accessing the memory is set in the channel (CH) identification register 11, and the CHP number to which the channel (CH) is connected is set in the CHP number identification section 12.

and a channel (CH) identification register 11;
The CHB tag sections (CHB TAG) 30 and 31 are accessed using the contents of the CHP number identification section 12 as an address, and the address section (ADDR) is read out, and in the comparison circuits (C) 40 and 41,
It is compared with the contents of the CHP address register (CHPAR)1.

According to the above comparison results, the fetish operation and the store operation are performed.
-095679, patent application 1982-091698, patent application 1982-166910
Since it is disclosed in et al., the description will be omitted, and only the parts related to the present invention will be explained below.

In the present invention, memory access from the CHP is
When UCW on MSU, flag signal “CHP
UCW flag 13
Using the flub signal set in
71 is set to off, and the following control is performed.

(a) In the case of “UCW fetish”.

Due to the above operation, the valid bit flags 70 and 70 always appear to be off, so the output signal of the UCW access flag 8 operates to perform fetch access to the MSU.

That is, the command to the MSU at this time is "8-byte access", and the 8-byte fetch data fetched from the MSU is not loaded into the CHB (in other words, the gate circuit GF is controlled by the output signal of UCW access flag 8). do,
CHP fetch data register (CHPFCHDR)
35) directly to the CHP and terminate the operation.

(b) In the case of “UCW Store”.

As in the case of the fetch operation described above, since the valid bit flag 70 always appears to be off,
An attempt is made to select and store a new block by referring to CHB tag sections (CHB TAG) 30 and 31, but due to UCW access, CHB
(In other words, the gate circuit GS is controlled by the output signal of UCW access flag 8, and the CHP store data register (CHPSTDR) is stored.
8) directly to the MSU.
Store the byte data and end the operation.

As described above, when the present invention is implemented and UCW access is performed, the CHB is not accessed, so the CHB contents do not change.

(g) Effects of the Invention As described above in detail, the memory access control circuit of the present invention allows the memory access control circuit of the present invention to
Focusing on the fact that the flag "CHP UCW" indicating UCW access is sent, using this flag signal,
directly without referencing (i.e. ignoring) CHB
Since it is designed to access MSU,
Input/output status area (UCW) access from the CHP does not change the contents of the CHB;
This has the effect of preventing a drop in slaput.

[Brief explanation of drawings]

Figure 1 shows CHB during continuous data transfer.
FIG. 2 is a block diagram showing an embodiment of the present invention. In the drawing, D0 to D15 are consecutive 8
Byte data numbers, 1 and 2 are CHP address register (CHPAR), 11 and 21 are channel (CH) identification registers, 12 and 22 are CHP number identification part, 13 is UCW flag, 30 and 31 are CHB tag part (CHB TAG), 32 is the data section (CHB
DATA), 40, 41 are comparison circuit C, 50, 51
is an AND circuit, 60 and 61 are tag part match registers, 70 and 71 are valid bit flags, and 8 is a
UCW access flag, 9 is converter (DEC), 1
01 to 103 are CHB data part (CHB DATA)
33 is a CHB data register (CHPDR), 34 is a CHP store data register (CHP STDR), 35 is a CHP fetch data register (CHPFC HDR), and GS and GF are gate circuits.

Claims (1)

[Claims] 1. A central processing unit (CPU), a channel processing unit (CHP) that controls multiple channels (CH),
Main storage unit (MSU) and main storage unit (MSU)
a memory control unit (MCU) that performs access control to and interface control between a central processing unit (CPU) and a channel processing unit (CHP);
In a data processing device having a channel buffer (CHB) between the main storage unit (MSU) and a channel processing unit (CHP), it is necessary to protect the order of data transfer from the channel (CH). Among the data and some control information, access to the general data is done through the channel buffer (CHB), and access to some of the control information is done by referring to the channel buffer (CHB). However, control information (UCW) that does not need to maintain order with the data transfer
1. A memory access control circuit having a function of directly accessing a main storage unit (MSU) without referring to the channel buffer (CHB).