JPS54128635A - Control system for cash memory - Google Patents

Control system for cash memory

Info

Publication number
JPS54128635A
JPS54128635A JP3609178A JP3609178A JPS54128635A JP S54128635 A JPS54128635 A JP S54128635A JP 3609178 A JP3609178 A JP 3609178A JP 3609178 A JP3609178 A JP 3609178A JP S54128635 A JPS54128635 A JP S54128635A
Authority
JP
Japan
Prior art keywords
memory
control
cash
cpu
directory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3609178A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Kobayashi
Takashi Rokutanda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3609178A priority Critical patent/JPS54128635A/en
Publication of JPS54128635A publication Critical patent/JPS54128635A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To perform the memory control with good efficiency, by changing the handling of the cash memory based on the nature of the memory access request from CPU and controlling the fixed area of the main memory with the output of the zero detector in accessing it.
CONSTITUTION: In the data processor having the cash memory 3, the CPU1 performing operation control, main memory 2, cash memory 3 temporarily entrying the read out data from the memory 2 or the write-in data in the memory 3, interleave control ILV performing refresh control for the memory 2, and the control section HBC controlling the high speed bus connected to the DMA unit. Further, when the CPU 1 makes access request, the memory 2 is accessed via the memory 3, and when the tag signal 8 representing that the CPU 1 is in input and output operation is outputted to the directory 9, the signal is detected with the zero detector provided with the directory 9 and the control section of the memory 3 is controlled to directly access the memory 2.
COPYRIGHT: (C)1979,JPO&Japio
JP3609178A 1978-03-30 1978-03-30 Control system for cash memory Pending JPS54128635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3609178A JPS54128635A (en) 1978-03-30 1978-03-30 Control system for cash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3609178A JPS54128635A (en) 1978-03-30 1978-03-30 Control system for cash memory

Publications (1)

Publication Number Publication Date
JPS54128635A true JPS54128635A (en) 1979-10-05

Family

ID=12460072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3609178A Pending JPS54128635A (en) 1978-03-30 1978-03-30 Control system for cash memory

Country Status (1)

Country Link
JP (1) JPS54128635A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246457A (en) * 1984-05-21 1985-12-06 Fujitsu Ltd Memory access controlling circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5187927A (en) * 1975-01-31 1976-07-31 Hitachi Ltd
JPS5242032A (en) * 1975-09-29 1977-04-01 Hitachi Ltd Data processing unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5187927A (en) * 1975-01-31 1976-07-31 Hitachi Ltd
JPS5242032A (en) * 1975-09-29 1977-04-01 Hitachi Ltd Data processing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246457A (en) * 1984-05-21 1985-12-06 Fujitsu Ltd Memory access controlling circuit
JPH0347542B2 (en) * 1984-05-21 1991-07-19 Fujitsu Ltd

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